Method of fabricating dynamic random access memory capacitor

Details Method of fabricating dynamic random access memory capacitor Method of fabricating dynamic random access memory capacitor

1998-11-25

2002-04-09

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000

Reexamination Certificate

active

06368908

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating a capacitor.
2. Description of the Related Art
As the function of a microprocessor becomes more powerful, the program and software calculations become more complicated, and thus the need for Dynamic Random Access Memory (DRAM) storage memory is increased. As the number of semiconductor devices incorporated in an integrated circuit increases, a memory cell, which comprises a transfer field effect transistor (TFET) and a storage capacitor, is widely used.
FIG. 1
is a circuit diagram of a DRAM memory cell. A capacitor C selected from an array of capacitors is used to store information as binary data by charging/discharging the capacitor C. Normally, a binary bit is stored in each capacitor. When the capacitor C is free of charge, logic “0” is represented, whereas when the capacitor is fully charged, logic “1” is represented. In general, a dielectric film
101
is deposited between a top electrode (cell electrode)
102
and a bottom electrode (storage electrode)
100
. The capacitor C is electrically coupled with a bit line BL. The read/write operations of a DRAM memory cell are performed by charging/discharging the capacitor C. The bit line BL is connected to the drain of a transfer field effect transistor T. The capacitor C is connected to the source of the transfer field effect transistor T. A signal is transmitted through a gate of the transfer field effect transistor T, which controls the capacitor C by turning on or off the connection with the bit line BL. In other words, the transfer field effect transistor T acts as a switch to control the charging or discharging the capacitor C.
In the DRAM manufacturing process, a two-dimensional capacitor called a planar type capacitor is mainly used for a conventional DRAM having a storage capacity less than 1M (mega=million) bits. In the case of a DRAM having a memory cell using a planar, type capacitor, electric charges are stored on the main surface of a semiconductor substrate, and thus the main surface is required to have a large area. This type of a memory cell is therefore not suited to a DRAM having a high degree of integration. For a highly integrated DRAM, such as a DRAM with more than 4M bits of memory, a three-dimensional capacitor, such as a stacked-type or a trench-type capacitor, has been introduced.
With stacked-type or trench-type capacitors, it has been made possible to obtain a larger memory in a similar Volume. However, to realize a semiconductor device of an even higher degree of integration, such as a very-large-scale integration (VLSI) circuit having, a capacity, of 64M bits, a capacitor of such a simple three-dimensional structure as the conventional stacked-type or trench-type, turns out to be insufficient.
One solution for improving the capacitance of a capacitor is to use a fin-type stacked capacitor. The fin-type stacked capacitor includes electrodes and dielectric layers which extend in a fin shape with a plurality of stacked layers. Hence, when the surface area of the electrode is enlarged, the capacitance is increased. Refer to Ema et al., “3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs”, International Electron Devices Meeting, pp. 592-595, December 1988, and the U.S. Pat. Nos. 5,071,783, 5,126,810, and 5,206,787.
Another solution for improving the capacitance of a capacitor is to use a cylindrical-type stacked capacitor. The cylindrical-type stacked capacitor includes electrodes and dielectric films which extend in a cylindrical shape to increase the surface areas of the electrodes. Refer to Wakamiya et al., Novel Stacked Capacitor Cell for 64-Mb DRAM. 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70, and the U.S. Pat. No. 5,077,688.
With the trend toward high integration density, the size of the DRAM cell must be further reduced. Generally, a reduction in the size of the cell leads to a reduction in charge storage capacitance. Additionally, as the capacitance is reduced, the likelihood of soft errors arising from the incidence of &agr;-rays is increased. Therefore, there is still a need in this art to design a new structure and methods for further increasing the capacitance of a storage capacitor, while reducing the area occupied by the capacitor in a plane.
SUMMARY OF THE INVENTION
Accordingly, the invention provides a fabricating method of a capacitor, which maintains the capacitance while decreasing the area occupied by the capacitor in a plane. The other purpose of the invention is to decrease the manufacturing costs, and increase process tolerance and product yield.
According to the invention, the method of fabricating a capacitor comprises the steps of forming a transistor on a substrate and forming a dielectric layer, an etching stop layer, and a stacked layer in sequence over the substrate. Preferably, the material of the etching stop layer includes silicon nitride. The stacked layer is formed from alternately arranged several conductive layers and isolation layers. Preferably, the material of the isolation layers of the stacked layer includes silicon oxide. Preferably, the material of the conductive layers of the stacked layer includes doped polysilicon. The etching stop layer is used as an etching stop point. The stacked layer is patterned to form an opening above the source/drain region of the transistor. A conductive spacer is formed on the sidewall of the stacked layer exposed by the opening. The conductive spacer is used as a mask. A portion of the etching stop layer and the dielectric layer exposed by the opening are removed to form a contact hole, which exposes the source/drain region. In the same step, the top isolation layer of the stacked layer is simultaneously removed to expose the top conductive layer of the stacked layer. A conductive layer is formed over the substrate to fill the contact hole. The conductive layer is electrically coupled with the source/drain region. The conductive spacer is covered by the conductive layer to form a raised region. A stacked spacer is formed beside the raised region. The stacked spacer is stacked by alternately forming several isolation layers and several conductive layers. The conductive layer and the stacked layer are patterned. The isolation spacers of the stacked spacer and the isolation layers of the stacked layer are removed to expose a storage electrode. The storage electrode is formed from the conductive layer and the conductive spacers.
In a further aspect of the invention, the etching rate of the etching stop layer is different from the etching rates of the conductive layer and the first isolation layers of the stacked layer. The etching rate of the isolation layers of the stacked layer is different from the etching rate of the conductive layers of the stacked layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5491103 (1996-02-01), Ahn et al.
patent: 5903430 (1999-05-01), Takaishi

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