Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-25
2002-05-21
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S305000
Reexamination Certificate
active
06391730
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates, generally, to methods for fabricating semiconductor devices and, more particularly, to methods for fabricating non-volatile semiconductor devices, such as EEPROM devices.
BACKGROUND OF THE INVENTION
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Typically, an EEPROM device includes a floating-gate electrode upon which electrical charge is stored. The floating-gate electrode overlies a channel region residing between source and drain regions in a semiconductor substrate. The floating-gate electrode together with the source and drain regions forms an enhancement transistor. By storing electrical charge on the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively high value. Correspondingly, when charge is removed from the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively low value. The threshold level of the enhancement transistor determines the current flow through the transistor when the transistor is turned on by the application of appropriate voltages to the gate and drain. When the threshold voltage is high, no current will flow through the transistor, which is defined as a logic 0 state. Correspondingly, when the threshold voltage is low, current will flow through the transistor, which is defined as a logic 1 state.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. Silicon nitride in combination with silicon dioxide is known to provide satisfactory dielectric separation between the control-gate electrode and the channel region of the enhancement transistor, while possessing electrical characteristics sufficient to store electrical charge. During programming, electrical charge is transferred from the substrate to the silicon nitride layer located in an oxide-nitride-oxide (ONO) layer.
Non-volatile memory designers have taken advantage of the ability of silicon nitride to store charge in localized regions and have designed memory circuits that utilize two regions of stored charge within the ONO layer. This type of non-volatile memory device is known as a two-bit EEPROM. The two-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left and right bit is stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell. Programming methods are then used that enable two-bits to be programmed and read simultaneously. The two-bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions.
These devices require pocket regions near the source and drain regions on either side of the channel. Electrons are sourced from the pocket regions and injected into the nitride layer. As devices are scaled to smaller dimensions, it becomes more difficult to form the pocket regions at precise locations in the channel region. While the recent advances in EEPROM technology have enabled memory designers to double the memory capacity of EEPROM arrays using two-bit data storage, numerous challenges exist in the fabrication of material layers within these devices. In particular, the pocket regions must be carefully fabricated to avoid excessive overlap with the source and drain regions. Accordingly, advances in fabrication technology are necessary to insure proper function two-bit EEPROM devices as device dimensions are scaled to smaller values.
SUMMARY OF THE INVENTION
The present invention is for a process of fabricating pocket regions in a non-volatile semiconductor device. The pocket regions are typically formed adjacent to and on either side of a buried-bit line in an EEPROM device. Improved device performance is attained at extremely small feature size by implanting molecular ions into the substrate to form the pocket regions. The use of molecular ions enables the pocket regions to be formed to have a relatively high dopant concentration, yet exhibit a very shallow junction depth (X
j
). As EEPROM devices are scaled to extremely small dimensions, it becomes necessary to reduce the junction depth of the doped regions that form source, drain, bit-line and channel regions in the substrate. A process carried out in accordance with the present invention enables devices within an EEPROM memory cell to be fabricated to extremely small dimensions, while maintaining optimum electrical performance.
In one form, a process for fabricating a non-volatile semiconductor device includes providing a semiconductor substrate having a patterned layer thereon. The patterned layer has an opening that exposes a bit-line region of the semiconductor substrate. Molecular ions are implanted into the substrate at an offset angle with respect to the normal of a principal surface of the substrate to form first and second pocket regions to a first junction depth. Then, a buried bit-line is formed in the bit-line region of the substrate to a second junction depth. The processing steps are carried out such that the second junction depth is greater than the first junction depth.
REFERENCES:
patent: 5943576 (1999-08-01), Kappor
patent: 6168993 (2001-01-01), Foote et al.
Halliyal Arvind
Kluth George J.
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Le Dung A
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