Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-11-06
2002-05-21
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S623000, C438S624000, C438S631000, C438S637000
Reexamination Certificate
active
06391764
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and in particular to a method for fabricating a semiconductor device which can improve electrical properties of the semiconductor device, by preventing short from occurring between an interconnection line and a metal electrode.
2. Description of the Background Art
Recently, integration of a semiconductor device has been remarkably improved. As a result, there is a strong demand for a method for easily fabricating a transistor and planarizing an interlayer insulating film to enhance the integration of the semiconductor device.
So as to maximize a planarization property, a method for improving the planarization property according to an etching process has been mostly performed on borophosphosilicate glass (BPSG) film used for planarization of the interlayer insulating film, after performing a flow (or reflow) process at a high temperature.
When performed at temperatures over 820° C., the high temperature flow process can improve the planarization property of the BPSG film. However, impurities are diffused into a gate electrode during the high temperature thermal treatment process, thereby degrades the performance properties of the semiconductor device.
In order to overcome this disadvantage, the flow process of the BPSG film must be performed at a temperature below 820° C. In flow processes at temperatures below 820° C., however, planarization of the BPSG film is generally not satisfactory.
Accordingly, an interconnection line formed on the interlayer insulating film having a poor planarization property is moved thereon during a succeeding thermal treatment process, and thus short may occur between the interconnection line and an adjacent metal electrode.
Even if the flow process is performed over 820° C. on the BPSG film to improve the planarization property, subsequent movement of the interconnection line is not completely avoided, which degrades the performance of the semiconductor device.
In this regard, a conventional method for fabricating a semiconductor device will now be described with reference to
FIGS. 1
to
4
.
FIG. 1
is a cross-sectional view illustrating the conventional method for fabricating the semiconductor device.
FIG. 2
is a cross-sectional view illustrating the conventional method for fabricating the semiconductor device in a state where short is generated between a polysilicon electrode and a metal electrode due to a movement resulting from the thermal treatment process.
FIGS. 3 through 6
are graphs respectively showing the relation between the movement range of the polysilicon electrode due to the thermal processes as a function of variations in the design rules, the steps of the thermal treatment process, the thermal treatment process temperature and the ratio of boron and phosphorus in the BPSG film are varied.
As illustrated in
FIG. 1
, an active region and a device isolating region are defined by forming a device isolating film
2
on a semiconductor substrate
1
.
A gate oxide film
3
, a gate conductive film
4
and a hard mask film
5
are sequentially stacked on the active region where the device isolating film
2
is not formed.
The gate oxide film
3
, gate conductive film
4
and hard mask film
5
are selectively patterned according to a photolithography and developing processes. Thereafter, spacers
7
are formed at the side portions of the patterned films, thereby forming a gate electrode.
On the other hand, the gate conductive film
4
and the hard mask film
5
are stacked on the active region where the device isolating film
2
is formed, and patterned in a predetermined shape. The spacers
7
are formed at the side portions of the patterned films to form the gate electrode.
A lightly-doped region
6
a
and a highly-doped region
6
b
are formed on the semiconductor substrate
1
of the active region, and thus a source region and a drain region are respectively defined.
A first interlayer insulating film having a stacked structure comprising a tetraethylorthosilicate (TEOS) oxide film
8
and a BPSG film
9
is formed on the gate electrode consisting of the gate oxide film
3
, gate conductive film
4
, hard mask film
5
and spacers
7
. A polysilicon electrode
10
is formed above to serve as an interconnection line (the gate electrode).
Then, a second interlayer insulating film
11
is formed on the first interlayer insulating film to cover the polysilicon electrode
10
.
A contact hole (not shown) is formed on the second interlayer insulating film
11
. A metal electrode
12
is formed on the second interlayer insulating film
11
and extending through the contact hole to contact the source/drain region
6
b
of the active region.
Here, the interconnection line may comprise WSi
x
, PtSi
x
, CoSi
x
, TiSi
x
, and/or WSi
x
/polysilicon.
In addition, the high temperature flow process is performed on the first interlayer insulating film to
8
,
9
improve the planarization property.
As described above, when the stacked structure comprising the TEOS oxide film
8
and the BPSG film
9
is employed as the first interlayer insulating film, the polysilicon electrode
10
moves along the BPSG film
9
during the succeeding thermal treatment process, as shown in
FIG. 2
(solid line), and may generate a short with the metal electrode
12
.
Especially in those cases in which the thermal treatment process is performed below 820° C., the resulting BPSG film
9
is not well planarized and, as a result, the polysilicon electrode
10
is often moved in adjacent regions having low pattern density.
FIG. 3
shows a movement range of the polysilicon electrode P
2
when the design rules of the semiconductor devices range from 0.18 to 0.55 &mgr;m and the thermal treatment process is performed at a temperature over 800° C. at least three times.
Referring to
FIG. 3
, the polysilicon electrode P
2
is moved on the BPSG film by at least 0.3 &mgr;m as a result of the thermal treatment process.
In the case of a high integration semiconductor device having a design rule of 0.25 &mgr;m, the interconnection line deposited on the BPSG film, such as the polysilicon electrode, is moved by more than 0.3 &mgr;m due to the thermal treatment process, and thus increasing the likelihood of a short forming between the interconnection line and the metal electrode.
As illustrated in
FIG. 4
, when the flow process is carried out on the BPSG film at a temperature over 820° C., the polysilicon electrode P
2
is moved by 0.2 &mgr;m as a result of a second thermal treatment process (second BPSG), and 0.35 &mgr;m as a result of a third thermal treatment process (third BPSG).
As described above, the movement range of the polysilicon electrode P
2
is increased by repetition of the thermal treatment process. Therefore, when a multi-step thermal treatment process is utilized, a short nearly always occurs between the polysilicon electrode P
2
and the metal electrode.
As shown in
FIG. 5
, when the first thermal treatment process is performed at temperatures of 800° C., 820° C. and 850° C., the polysilicon electrode P
2
is moved by about 0.35 &mgr;m, 0.31 &mgr;m and 0.3 &mgr;m, respectively.
Referring to
FIG. 6
, the movement range of the polysilicon electrode P
2
on the BPSG film varies according to the content ratio of boron and phosphorus in the BPSG film being subjected to the high temperature flow process.
That is, when the flow process is performed at 850° C., the movement range of the polysilicon layer is larger when a content ratio of boron to phosphorus is 4.5:4.2 (71) than when it is 4.0:4.2 (72).
However, in either case, the polysilicon electrode P
2
is moved by more than 0.3 &mgr;m.
As a result, when the thermal treatment process is performed below 820° C. to prevent diffusion, and when the flow process is executed over 820° C. to planarize the BPSG film, the polysilicon electrode P
2
is moved by at least 0.3 &mgr;m as a result of the multi-step thermal treatment process.
Degradation of the semiconductor device resulting from t
Hyundai Electronics Industries Co,. Ltd.
Pham Long
Pillsbury & Winthrop LLP
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