Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Electron beam imaging
Reexamination Certificate
2000-07-12
2002-09-03
Huff, Mark F. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Electron beam imaging
C430S311000, C430S394000, C430S396000, C430S942000, C250S492200
Reexamination Certificate
active
06444398
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor manufacturing, and more particularly to, a process for forming features on a semiconductor wafer using a SCattered Angular Limited Projection E-Beam Lithography (SCALPEL) process.
BACKGROUND OF THE INVENTION
One goal in modern semiconductor fabrication is to improve the density of active elements provided on a single semiconductor die, thus increasing the number of die per wafer. As is known in the art, very large scale integration (VLSI) has evolved into ultra-high large scale integration (ULSI) where tens or hundreds of millions of active elements and devices are placed into a single integrated circuit (IC) die. This density is obtained by currently making devices that have a smallest-possible physical device dimension (i.e., critical dimension (CD)) on the order of 0.18 micron. In order to continue to improve this density without significantly increasing die size, and more importantly, to continue to improve device speed, there is a desire to further decrease the critical dimensions (CDs) of active elements and other devices on the semiconductor die beyond 0.18 micron.
Lithographic techniques are typically used in the formation of multi-level circuits on a semiconductor die. Currently, lithographic techniques take advantage of i-line (365 nanometer) and deep ultra-violet (DUV, 248 nanometer) energy sources to make 0.25 to 0.18 micron device dimensions. By decreasing wavelength of the energy utilized in these lithographic techniques, smaller active elements and transistors may be realized by enabling the creation of smaller critical dimensions (CDs). Accordingly, smaller wavelength, higher energy sources have been investigated for lithographic use in the IC industry, including deep ultra-violet (DUV) (193 nanometers), extreme ultra violet (EUV), approximately 11.0 to 13.4 nanometers), and X-ray sources.
Another lithographic technique, projection electron beam lithography (EBL), shows potential in meeting the future needs of the IC industry, including increased throughput and fine critical dimension (CD) control. In general, a projection electron-beam lithography system scans a beam at extremely high speeds across a masked surface to create an image on a semiconductor device. Electron optics can be inserted in the E-beam path to provide a means of advantageous image reduction. One specific type of projection electron beam lithography is known as SCattering with Angular Limitation in Projection Electron-Beam Lithography (SCALPEL). The basic principles of the SCALPEL technique are illustrated in prior art FIG.
1
.
Turning to
FIG. 1
, the basic principles of SCALPEL are illustrated. As shown, a mask
10
having a patterned scattering layer
14
is provided on membrane
12
, through which an electron beam (E-beam) is projected as represented by the arrows at the far left of FIG.
1
. Particularly, the patterned scattering layer
14
contains material having a higher atomic number than that of the membrane
12
. The scattering effect of the electron beam through portions of the mask is illustrated in
FIG. 1
between membrane
12
and a lens
20
. As shown, those portions of the electron beam that pass through the scattering layer
14
tend to be scattered to a greater extent as compared with those portions of the E-beam that pass through the membrane material having no overlying scattering layer
14
.
In
FIG. 1
, the electron beam passes through the mask
10
and is focused through an electron focusing system, represented by lens
20
. The electron beam (E-beam) then passes through back focal plane filter
30
. The filter
30
has an aperture that is provided to permit passage of those portions of the electron beam that were not scattered by the scattering layer of the mask
10
. In other words, beams that were scattered at or greater than some finite threshold angle are not passed through the filter
30
while all beams having a scattering angle at less than the some finite threshold angle are passed by the filter
30
. The portion of the electron beam passing through the filter
30
is then projected onto a semiconductor wafer
40
having a plurality of die
42
and a resist layer
44
formed thereon. The resist layer is formed by conventional techniques such as by spin coating and baking processes.
The electron beam forms an image in the photoresist of the wafer
40
. The image includes areas of high exposure intensity formed by those portions of the electron beam that pass between patterned portions
14
of the mask
10
, and areas of relatively low exposure intensity formed by those portions of the electron beam that pass through the patterned areas
14
of the mask
10
. Therefore, via a light scattering technique, a high-resolution image may be projected onto the resist layer
44
, which is then developed to form a patterned resist layer
44
as shown in FIG.
1
. Thereafter, the material exposed through the patterned resist layer may be etched or developed using an appropriate etchant. It is noted that the power of the system may be adjusted so as to provide a 3-5× reduction in image size, typically 4× is a common image reduction size.
Turning to
FIG. 2
, a top perspective plan view of the mask
10
of
FIG. 1
is illustrated. Mask
10
illustrates four adjacent windows, where one window is labeled as window
50
. It is noted that typically an array of windows, such as a 8-by-60 array of windows, are formed on a wafer where many more than just the four representative windows in
FIG. 2
are formed on the mask
10
. In essence, only four windows
50
in
FIG. 4
are provided in
FIG. 2
for ease of illustration. Each window
50
includes a data field region
52
bounded by a skirt region
54
. As illustrated, a plurality of patterned features
48
, which make up the scattering layer
14
are formed within the data field region
52
. During patterning, exposure of the windows
50
is “stepped” over a surface of a semiconductor device in X-Y location increments, so as to form a contiguous pattern
60
, as illustrated in FIG.
3
. Each of the windows
50
is butted or stitched together via fine lithographic alignments such that the contiguous pattern
60
is formed from the segmented mask windows
50
of FIG.
2
. In this regard, the separated windows in
FIG. 2
are slightly overlapped with each other as indicated by the dotted lines
58
in
FIG. 3
in order to form the contiguous pattern on the wafer. The overlapping of the windows
50
during exposure forms first overlap region
58
a
and second overlap region
58
b
which intersect each other at multiple overlap region
50
c.
Along first overlap region
58
a
, and along second overlap region
58
b
, the semiconductor device is subjected to energy exposure two times or 2× the typical exposure. Along multiple overlap region
50
c
, the semiconductor wafer is exposed to the electron beam four times and therefore receives 4× the normal exposure due to overlapping of windows
50
during E-beam exposure.
The present inventor has recognized that multiple exposures along overlap regions
58
a
-
58
b
and
50
c
are problematic. Particularly, as is understood in the art, the materials provided for formation of the scattering layer
14
to form the patterned features
48
is effective to provide an image contrast on the order of 5 to 6. In other words, the portions of the semiconductor device corresponding to the patterned features
48
receive ⅕th to ⅙th the intensity of the electron beam as compared to unpatterned regions or unmasked portions of the mask
10
. According, exposure at multiple overlap region
50
c
becomes problematic, since multiple overlap region
50
c
receives a ⅕th dose of electrons four times (4×), which tends to result in an unwanted definition of a feature on the substrate in this multiple overlap region
50
c.
A further problem with this prior art process is illustrated in connection with FIG.
4
. As illustrated, window
50
includes first and second patterned features
Barreca Nicole
Huff Mark F.
Motorola Inc.
Rodriguez Robert A.
Witek Keith E.
LandOfFree
Method for manufacturing a semiconductor wafer using a mask... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing a semiconductor wafer using a mask..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a semiconductor wafer using a mask... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2907957