Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-13
2002-08-27
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S286000, C438S253000, C438S255000
Reexamination Certificate
active
06440799
ABSTRACT:
TECHNICAL FIELD
The invention pertains to methods of implanting dopants into semiconductor structures, and in particular embodiments pertain to methods of forming CMOS constructions. The invention also pertains to semiconductor structures.
BACKGROUND OF THE INVENTION
It is common for semiconductor structures to comprise p-channel devices adjacent n-channel devices. For instance, static random access memory (SRAM) and logic devices frequently comprise p-channel transistor devices adjacent n-channel transistor devices, or in other words frequently comprise PMOS devices adjacent NMOS devices. A construction comprising PMOS and NMOS devices can be referred to as a CMOS construction.
A prior art method for fabricating a CMOS construction is described with reference to
FIGS. 1-4
. Referring initially to
FIG. 1
, a fragment
10
of a semiconductor construction is illustrated. Fragment
10
comprises a substrate
12
having a dielectric material
14
and a semiconductive material
16
provided thereover. Substrate
12
can comprise, for example, monocrystalline silicon; dielectric material
14
can comprise, for example, silicon dioxide; and semiconductive material
16
can comprise, for example, either amorphous or polycrystalline silicon.
For purposes of the discussion that follows, the semiconductive material of substrate
12
can be referred to as a first semiconductive material, and the semiconductive material
16
can be referred to as a second semiconductive material. Additionally, fragment
10
can be referred to as a semiconductor structure. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
A dashed line
18
subdivides fragment
10
into a pair of defined regions
20
and
22
, with one of the regions ultimately being utilized for PMOS constructions and the other of the regions ultimately being utilized for NMOS constructions. Dashed line
18
can be considered an imaginary boundary segregating regions
20
and
22
from one another.
Referring to
FIG. 2
, semiconductor fragment
10
is illustrated in top view, wherein it is shown that semiconductive material
16
and dielectric material
14
are patterned into the shape of a line (dielectric material
14
is not visible in the view of FIG.
2
), with such line extending across regions
20
and
22
. It is noted that the line can extend entirely across regions
20
and
22
, or can extend only partially across one or both of regions
20
and
22
. Semiconductive material
16
can ultimately be utilized to form gates for transistor devices associated with regions
20
and
22
.
Referring to
FIG. 3
, a photoresist mask
24
is shown formed over region
22
, while leaving region
20
uncovered. Mask
24
can be formed by photolithographic processing methods. Specifically, mask
24
can be formed by initially providing a layer of photoresist across both regions
20
and
22
, and subsequently exposing the photoresist to a patterned beam of radiation. The patterned beam of radiation selectively exposes the photoresist over one of regions
20
and
22
to the radiation, while leaving the photoresist over the other of regions
20
and
22
not exposed. A solvent can then be utilized to selectively remove the photoresist from over region
20
, while leaving the photoresist over region
22
. The photoresist utilized for forming mask
24
can be either positive photoresist or negative photoresist, and accordingly it can be either the portion over region
20
which is selectively exposed to radiation, or the portion over region
22
which is selectively exposed to radiation.
After patterned mask
24
is formed, fragment
10
is exposed to a first dopant implant. The dopant of the first implant is illustrated by downwardly extending arrows
26
. The dopant can be either n-type or p-type conductivity-enhancing dopant, and can be implanted to be primarily within either substrate
12
or semiconductive material
16
of region
20
. For instance, if region
20
is ultimately to comprise a PMOS device, dopant
26
can comprise n-type conductivity-enhancing dopant and can be implanted to form an n-type doped region
28
within substrate
12
.
A second dopant
30
is implanted after the implant of first dopant
26
, and is provided to be primarily in either semiconductive material substrate
12
or semiconductive material
16
; and will be provided to be primarily in whichever of materials
12
and
16
did not primarily contain the implant of dopant
26
. Accordingly, if dopant
26
was primarily directed into semiconductive substrate
12
, dopant
30
will be primarily directed into semiconductive material
26
to form an implant
32
within material
26
. If region
20
is ultimately to be utilized for forming a PMOS device, implant
32
can comprise p-type dopant.
It is to be understood that dopants
26
and
30
can both be implanted into both of semiconductive substrate
12
and semiconductive material
16
; however, the dopants will typically be implanted to a heavier concentration in one of either the substrate
12
or material
16
than in the other of the substrate
12
and material
16
. In the shown embodiment, first dopant
26
is implanted to a heavier concentration in semiconductive substrate
12
than in semiconductive material
16
, and second dopant
30
is implanted to a heavier concentration in semiconductive material
16
.
Mask
24
protects region
22
from receiving either of dopants
26
or
30
therein.
Referring to
FIG. 4
, patterned mask
24
(
FIG. 3
) is removed, and a second patterned mask
33
is formed. Mask
33
covers region
20
, while leaving region
22
exposed. Mask
33
can be formed by processing similar to that described above with reference to mask
24
.
After mask
33
is formed, a first dopant
34
is implanted into region
22
. Dopant
34
can be either an n-type or p-type dopant, and can be provided primarily into either semiconductive substrate
12
or semiconductive material
16
. If region
22
is ultimately to be utilized for forming an NMOS device, dopant
34
can comprise p-type dopant, and can be provided primarily into semiconductive substrate
12
to form a doped region
36
.
After the implant of dopant
34
, a second dopant
38
is implanted into region
22
. Second dopant
38
is directed into whichever of semiconductive material
16
and semiconductive substrate
12
did not primarily receive the implant of first dopant
34
. Accordingly, in the shown embodiment dopant
38
can be utilized to form an implant region
40
within semiconductive material
16
. If region
22
is ultimately to be utilized for forming an NMOS device, dopant
38
can comprise an n-type dopant, and can accordingly be utilized to dope semiconductive material
16
of region
22
to n-type conductivity type.
A solid boundary replaces dashed line
18
within semiconductive material
16
and substrate
12
of
FIGS. 3 and 4
to indicate that a border extends along the line
18
within materials
16
and
12
. The border within material
16
delineates a boundary where dopant regions
32
and
40
meet; and the border within substrate
12
delineates a boundary where dopant regions
28
and
36
meet.
A problem which can occur during the prior art processing of
FIGS. 1-4
is that dopant can migrate between doped regions
32
and
40
during subsequent thermal processing of fragment
10
. For instance, if region
32
is a p-type doped region and region
40
is an n-type doped region, it is found that n-type dopant from region
40
can migrate into region
32
and change the electrical charac
Lebentritt Michael S.
Wells St. John P.S.
LandOfFree
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