Clock-delayed pseudo-NMOS domino logic

Details Clock-delayed pseudo-NMOS domino logic Clock-delayed pseudo-NMOS domino logic

2000-08-30

2002-04-16

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S096000, C326S097000

Reexamination Certificate

active

06373290

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor logic devices, and, more particularly, to clocked static logic useful for high frequency operations.
2. Description of the Related Art
Integrated circuitry to implement various logic functions is well known in the semiconductor industry. The use of transistors, capacitors and other integrated circuit elements to implement AND, OR, NAND, NOR, NOT, and other logical operations is well known in that art, and logic circuitry itself has taken on many forms. For example, logic circuitry has been implemented in NMOS technologies as well as in CMOS technologies, each with its own advantages and disadvantages. Moreover, logic circuitry may be implemented in dynamic or static, clocked or not clocked, circuitry. CMOS logic is preferred in many applications because of its relatively low power dissipation, as compared to, for example, NMOS logic.
FIG. 1
shows a standard two-input CMOS static logic NOR gate
10
, while
FIG. 2
shows a two-input pseudo-NMOS static logic NOR gate
30
. The CMOS static logic gate
10
of
FIG. 1
includes two PMOS transistors
12
,
14
and two NMOS transistors
16
,
18
. A capacitive load
20
exists on an output line
26
. A signal on input line
22
is applied to the gate of the PMOS transistor
14
and to the gate of the NMOS transistor
18
, while a signal at input line
24
is applied to the gate of the PMOS transistor
12
and to the gate of the NMOS transistor
16
. The pseudo-NMOS gate
30
of
FIG. 2
includes one PMOS transistor
32
and two NMOS transistors
36
,
38
. The gate of the PMOS transistor
32
is coupled to a ground potential
34
, while signals at input lines
42
,
44
are applied to the gates of the NMOS transistors
36
and
38
, respectively. Again, a capacitive load
40
exists on the output line
46
. The pseudo-NMOS gate
30
, as compared to the CMOS static gate
10
of
FIG. 1
, has fewer devices and much less wiring complexity, and it yields comparable performance and consumes comparable power at high clock frequencies. However, the pseudo-NMOS gate
30
of
FIG. 2
does dissipate DC power. Both the CMOS static logic gate
10
of FIG.
1
and the pseudo-NMOS gate
30
of
FIG. 2
are well known to persons of ordinary skill in the art.
Pseudo-NMOS logic is a fully static logic family, and, like regular CMOS static logic systems with many logic levels, there may be many unnecessary switching transients before the data becomes stable and valid at the output. Clocked and/or dynamic logic systems can be employed to avoid these internal and unnecessary switching transients. In these systems, the signals are clocked through the system, and no evaluation is done at any logic gate until all the input signals arrive at the input terminals in the same time period. Only then is the logical decision made and the output signal determined and clocked forward to the next logic level.
One type of logic, commonly known as domino logic, offers certain advantages over static CMOS technology while retaining desirable low power dissipation characteristics. Domino logic gates may use either p-channel transistors or n-channel transistors for evaluating and realizing the Boolean function. Compared to CMOS circuits, domino logic reduces the number of devices required to implement a particular function, leading to reduced capacitive loading and circuit size. Domino logic has achieved widespread use in integrated circuits. With domino logic, a standard cell formed with a plurality of transistors represents a stage. A plurality of the stages can be cascaded or connected in series to implement the domino logic. A signal delivered to the first stage is evaluated, and the first stage produces an output signal that propagates to the second stage where the output signals of the first stage are evaluated. The second stage then produces additional output signals that, in turn, are propagated to the third stage wherein they are evaluated, and so on.
One feature of at least some forms of domino logic is that signals can propagate through the various stages without being separately clocked at each stage. Thus, a single clock cycle can be used to initiate the propagation of input signals through a plurality of cascaded stages, which collectively represent a relatively complex function. This avoids the need for high speed clocks to implement relatively complex functions, by avoiding the need for plural clock cycles to process the input signals. At the same time, the evaluation of the input signals within a single clock cycle provides relatively fast signal processing.
But despite these advantages, domino logic does have certain drawbacks. For example, where domino logic is implemented using MOS technology, certain functions are difficult to implement because they require the use of inverting logic functions (e.g., NOR, NOT, NAND functions). Instead, conventional MOS-implemented domino logic is generally limited to non-inverting gates to implement a function (e.g., AND, OR and so forth).
FIG. 3A
shows a well-known CMOS domino logic circuit
50
which, in part, works on dynamic logic principles. The circuit
50
includes a PMOS transistor
68
that serves to pre-charge the capacitive load
66
, and an NMOS transistor
70
that serves to enable the circuit
50
. An exemplary logic function
52
is shown in FIG.
3
and comprises three NMOS transistors
54
,
56
,
58
that receive input signals on lines
60
,
62
,
64
, respectively. Of course, any of a variety of different logic functions may be implemented in the logic function
52
. The PMOS transistor
68
is coupled between a power supply potential
73
and a node
75
of the logic function
52
, and the NMOS transistor
70
is coupled between the logic function
52
and a ground potential
67
. Each of the PMOS transistor
68
and the NMOS transistor
70
receive a signal “phi” at its gate terminal.
FIG. 3B
illustrates the two phases of the signal “phi”: a low potential during the pre-charge phase (between times t
1
and t
2
), and a high potential during the evaluation phase (between times t
2
and t
3
).
During the pre-charge phase, the low signal “phi” will cause the transistor
68
to conduct, thereby charging the load capacitance
66
to approximately the value of the supply voltage
73
. The non-conducting transistor
70
will prevent discharge of the load capacitance
66
during the pre-charge phase. At the end of the pre-charge phase and the beginning of the evaluation phase, the transistor
68
will stop conducting, and the transistor
70
will be turned on. If the logic function
52
results in a conductive path (signals on lines
60
,
62
are both high, or signal on line
64
is high), the load capacitance
66
will be discharged during the evaluation period. CMOS domino logic requires an inverter on the output of each gate to avoid a potential race condition where the output signal races forward from one gate to the next, resulting in logic errors. The inverter
78
serves to insure that after pre-charge, the output of each gate
50
is low and none of the NMOS transistors performing logic functions in the next gate
88
will be turned on. While this logic family has no DC power dissipation, it incorporates extra transistors and signal delays in the inverter
78
.
A number of different systems exist aside from standard two-phase dynamic CMOS logic. For example, sequentially clocked domino logic is illustrated in U.S. Pat. No. 5,402,012, issued Mar. 28, 1995, entitled “Sequentially Clocked Domino Logic Cells.” Wave propagation logic is illustrated in U.S. Pat. No. 5,532,625, issued Jul. 2, 1996, entitled “Wave Propagation Logic.” Clock-delayed domino logic is discussed in Yee and Sechen, “Clock-Delayed Domino for Adder and Combinational Logic Design,” ICCD 96, Oct. 7-9, 1996. Standard two-phase dynamic logic requires the generation of two clock signals, which are used to drive large capacitive loads. This is avoided in the latter three logic families by using clock signals that are pas

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