Chemistry: electrical and wave energy – Processes and products – Coating – forming or etching by sputtering
Reexamination Certificate
2000-10-10
2002-07-02
McDonald, Rodney G. (Department: 1753)
Chemistry: electrical and wave energy
Processes and products
Coating, forming or etching by sputtering
C204S192120
Reexamination Certificate
active
06413383
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to sputtering. In particular, the invention relates to the sputter deposition of copper in the formation of semiconductor integrated circuits.
BACKGROUND ART
Semiconductor integrated circuits typically include multiple levels of metallization to provide electrical connections between the large number of active semiconductor devices. Advanced integrated circuits, particularly those for microprocessors, may include five or more metallization levels. In the past, aluminum has been the favored metallization, but copper has been developed as a metallization for advanced integrated circuits.
A typical metallization level is illustrated in the cross-sectional view of
FIG. 1. A
lower-level layer
10
includes a conductive feature
12
. If the lower-level layer
10
is a lower-level dielectric layer, such as silica or other insulating material, the conductive feature
12
may be a lower-level copper metallization, and the vertical portion of the upper-level metallization is referred to as a via since it interconnects two levels of metallization. If the lower-level layer
10
is a silicon layer, the conductive feature
12
may a doped silicon region, and the vertical portion of the upper-level metallization is referred to as a contact because it electrically contacts silicon. An upper-level dielectric layer
14
is deposited over the lower-level dielectric layer
10
and the lower-level metallization
12
. There are yet other shapes for the holes including lines and trenches. Also, in dual damascene and similar interconnect structures, as described below, the holes have a complex shape. In some applications, the hole may not extend through the dielectric layer. The following discussion will refer to only via holes, but in most circumstances the discussion applies equally well to other types of holes with only a few modifications well known in the art.
Conventionally, the dielectric is silicon oxide formed by plasma-enhanced chemical vapor deposition (PECVD) using tetraethylorthosilicate (TEOS) as the precursor. However, low-k materials of other compositions and deposition techniques are being considered, and the invention is equally applicable to them. Some of the low-k dielectrics being developed can be characterized as silicates, such as fluorinated silicate glasses. Hereafter, only silicate (oxide) dielectrics will be directly described, but the invention is applicable in large part to other dielectric compositions.
A via hole is etched into the upper-level dielectric layer
14
typically using, in the case of silicate dielectrics, a fluorine-based plasma etching process. In advanced integrated circuits, the via holes may have widths as low as 0.18 &mgr;m or even less. The thickness of the dielectric layer
14
is usually at least 0.7 &mgr;m, and sometimes twice this, so that the aspect ratio of the hole may be 4 or greater. Aspect ratios of 6 and greater are being proposed. Furthermore, in most circumstances, the via hole should have a vertical profile.
A liner layer
16
is conformally deposited onto the bottom and sides of the hole and above the dielectric layer
14
. The liner
16
performs several functions. It acts as an adhesion layer between the dielectric and the metal since metal films tend to peel from oxides. It acts as a barrier against the inter-diffusion between the oxide-based dielectric and the metal. It may also act as a seed and nucleation layer to promote the uniform adhesion and growth and possibly low-temperature reflow for the deposition of metal filling the hole and to nucleate the even growth of a separate seed layer.
A metal layer
18
, for example, of copper is then deposited over the liner layer
16
to fill the hole and to cover the top of the dielectric layer
14
. Conventional aluminum metallizations are patterned into horizontal interconnects by selective etching of the planar portion of the metal layer
18
. However, a preferred technique for copper metallization, called dual damascene, forms the hole in the dielectric layer
14
into two connected portions, the first being narrow vias through the bottom portion of the dielectric and the second being wider trenches in the surface portion which interconnect the vias. After the metal deposition, chemical mechanical polishing (CMP) is performed which removes the relatively soft copper exposed above the dielectric oxide but which stops on the harder oxide. As a result, multiple copper-filled trenches of the upper level, similar to the conductive feature
12
of the next lower level, are isolated from each other. The copper filling the trenches acts as horizontal interconnects between the copper-filled vias. The combination of dual damascene and CMP eliminates the need to etch copper. Several layer structures and etching sequences have been developed for dual damascene, and other metallization structures have similar fabrication requirements.
Filling via holes and similar high aspect-ratio structures, such as experienced in dual damascene, has presented a continuing challenge as their aspect ratios continue to increase. Aspect ratios of 4:1 are common, and the value will further increase. An aspect ratio is defined as the ratio of the depth of the hole to the narrowest width of the hole, usually near its top surface. Via widths of 0.18 &mgr;m are also common, and the value will further decrease. For advanced copper interconnects formed in oxide dielectrics, the formation of the barrier layer tends to be distinctly separate from the nucleation and seed layer. The diffusion barrier may be formed from a bilayer of Ta/TaN, W/WN, or Ti/TiN, or of other structures. Barrier thicknesses of 10 to 50 nm are typical. For copper interconnects, it has been found necessary to deposit one or more copper layers to fulfill the nucleation and seed functions. The following discussion will address the formation of the copper nucleation and seed layer as well as the final copper hole filling.
The deposition of the metallization by conventional physical vapor deposition (PVD), also called sputtering, is relatively fast. A DC magnetron sputtering reactor has a target composed of the metal to be sputter deposited and which is powered by a DC electrical source. The magnetron is scanned about the back of the target and projects its magnetic field into the portion of the reactor adjacent the target to increase the plasma density there to thereby increase the sputtering rate. However, conventional DC sputtering (which will be referred to as PVD in distinction to other types of sputtering to be introduced) predominantly sputters neutral atoms. The typical ion densities in PVD are less than 10
9
cm
−3
. PVD also sputters atoms into a wide angular distribution, typically having a cosine dependence about the target normal. Such a wide distribution is disadvantageous for filling a deep and narrow via hole
22
illustrated in
FIG. 2
, in which a barrier layer
24
has already been deposited. The large number of off-angle sputter particles cause a copper layer
26
to preferentially deposit around the upper corners of the hole
22
and form overhangs
28
. Large overhangs further restrict entry into the hole
22
and at a minimum cause inadequate coverage of the sidewalls
30
and bottom
32
of the hole
22
. At worst, the overhangs
28
bridge the hole
22
before it is filled and create a void
34
in the metallization within the hole
22
. Once a void
34
has formed, it is almost impossible to reflow it out by heating the metallization to near its melting point. Even a small void introduces serious reliability problems. If a second copper deposition step is planned, such as by electroplating, the bridged overhangs make it impossible.
One approach to ameliorate the overhang problem is long-throw sputtering in a conventional reactor. In long-throw sputtering the target is spaced relatively far from the wafer being sputter coated. For example, the target-to-wafer spacing is at least 50% of wafer diameter, preferably is more than 90%, and more preferably is more than 140%. A
Chiang Tony P.
Cong Yu D.
Ding Peijun
Fu Jianming
Tang Howard H.
Cantelmo Gregg
Guenzer, Esq. Charles S.
McDonald Rodney G.
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