Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-03-27
2002-05-07
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S194000, C365S233500
Reexamination Certificate
active
06385078
ABSTRACT:
This application claims priority from Korean Patent Application No. 2000-25100, filed on May 10, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuit (IC) devices, and more particularly to a ferroelectric random access memory (FRAM) device.
BACKGROUND OF THE INVENTION
In recent years, a non-volatile memory which holds data even in a power-off state has been realized by using a ferroelectric material having a hysteresis characteristic such as PZT. More recent work with ferroelectric-based random access memory devices (FRAM) have shown many advantages over other memory technologies: FRAM is able to operate in high-speed with low-voltage, ferroelectric-based memories do not require an overly complicated construction, and FRAMs allow non-volatile storage.
The operational speed of FRAM is typically dependent upon the time it takes the ferroelectric material to undergo a polarization reversal. The polarization reverse speed is dependent on a square measurement of capacitor plates and the thickness of the ferroelectric thin film used to form the FRAM as well as the voltage applied to the device. Experiments have shown that FRAM is far faster than other non-volatile technologies such as EEPROM or flash memory.
FIG. 1
is a block diagram of a conventional FRAM device. The FRAM includes a memory cell array
10
that includes a plurality of memory cells (MC) that are arranged in rows and columns.
FIG. 1
shows a section of one of these memory cell rows, where each cell is comprised of an access transistor
11
(or a switching transistor) and a ferroelectric capacitor
12
. One memory cell composed of one transistor and one capacitor (1T/1C) stores one bit of data. The access transistor
11
includes a drain connected to an electrode of the ferroelectric capacitor
12
, a source connected to a column/bit line (BL), and a gate coupled with a row/wordline (WL). The other electrode of the ferroelectric capacitor
12
is connected with a late line (PL). Wordlines WLs and plate lines PLs arranged in the memory cell array are connected to a row main decoder
20
.
FIG. 2
a plot of a hysteresis loop showing a characteristic of the ferroelectric material used between the ferroelectric capacitor
12
electrodes. The abscissa (axis P) represents a potential difference between two electrodes of the ferroelectric capacitor, i.e. a voltage across the plates of the capacitor. The ordinate (axis V) represents a quantity of electric charge retained on a surface of the ferroelectric material by spontaneous polarization where the polization is expressed as &mgr;C/cm
2
units.
In an operation of a memory cell, if the ferroelectric material of a ferroelectric capacitor is in an initial state wherein zero volts is applied, the magnetic domains within the material retain an non-uniform state, and are not directed to any particular polarity. If a positive voltage is applied across the capacitor, however, then the capacitor will conduct current and move to a new positive polarization point A. At point A, the quantity of charge held in the ferroelectric material (i.e. the polarization) is Qs, and the voltage across the capacitor is the operating voltage Vcc. Thereafter, when the voltage across the capacitor returns to zero, the polarization only decreases slightly to point B rather than falling completely to zero. The ferroelectric material thus retains a residual polarization of Qr when the voltage across the ferroelectric capacitor is reduced to zero.
Next, if a negative voltage is applied across the capacitor, the polarization degree moves from point B to a negative charge polarization region shown in
FIG. 2
at point C, where all domains of the ferroelectric material are oppositely polarized to that at point A. Here, the polarization is indicated −Qs, and the voltage across the capacitor is −Vcc. Thereafter, when the voltage returns to zero, the polarization moves only slightly to point D rather than falling to zero. Here, the residual polarization thereof is indicated as −Qr. If the voltage again later increases to the positive level, the polarization of the ferroelectric material moves from point D to point A.
FRAMs thus exhibit non-volitile memory characteristics. Once a voltage for generating an electric field is applied to the ferroelectric capacitor with a ferroelectric material positioned between two electrodes, the polarization level is maintained even when the electrodes are established on a floating state. There is no natural loss caused from such a leakage in the surface charge of the ferroelectric material. Accordingly, the polarization level is retained so long as a voltage in opposite level is not applied for the polarization to be zero.
Returning to
FIG. 1
, the FRAM device further includes a row address latch circuit
30
, a column address latch circuit
40
, a row pre-decoder circuit
50
, a column decoder circuit
60
, a chip enable buffer circuit
70
, a read/write control circuit
80
, a sense amplifier circuit
90
, a data output buffer & write driver circuit
100
, and an input/output latch circuit
110
. The row pre-decoder circuit
50
and a column decoder circuit
60
comrpise a row decoder circuit.
FIG. 3A
is a timing diagram showing a normal operation of the FRAM device. In a circuit operation, the chip enable buffer circuit
70
enables a chip enable flag signal ICE to transition from a low level to a high level in response to a high-to-low transition of a external chip enable signal XCEB. A high level ICE signal causes each of the row and column address latch circuits
30
and
40
to latch a corresponding valid address. The row pre-decoder circuit
50
and the row main decoder circuit
20
enable a row or a wordline WL corresponding thereto in response to a row address RAi/RAiB (i≧1) which is latched in the row address latch circuit
30
.
Next, as shown in
FIG. 3A
, a plate line PL corresponding to the selected row or the enabled wordline is activated. It causes thereby the ferroelectric capacitors of the memory cells connected to the selected wordline to have the polarization at point D shown in FIG.
2
. The sense amplifier circuit
90
amplifies the voltages on each of the bit lines in response to a control signal SAEN provided from the read/write control circuit
80
. The data output buffer of the data output buffer & write driver circuit
100
provides the amplified voltages on the columns or the bit lines selected by the column decoder circuit
60
to the outside as a read data. After the external chip enable signal XCEB is disabled (transitioning from a low level to a high level), the plate line PL disabled thereby disabling the control signal SAEN, the chip enable flag signal ICE, the outputs of the row address latch circuit
30
, and the wordline WL. With those signals disabled, the read/write operation is terminated.
The latches in the FRAM device for latching a current memory address are controlled by the chip enable flag signal ICE, which in turn is activated by a high-to-low transition of the external chip enable signal XCEB. It is thus critical to the proper operation of this type of conventional FRAM that the ICE signal be activated at the correct time. It is important to understand, however, that the generated signal ICE maintains an enable state for a predetermined time regardless of a subsequent change of the external chip enable signal XCEB because a predetermined time is required for restoring the original data which has been damaged by a destructive read operation of the FRAM device. Accordingly, the chip enable flag signal ICE will be disabled in conventional FRAM devices only when two events occur: (1) the predetermined amount of time has passed and (2) the external chip enable signal XCEB is disabled.
FRAM devices designed in this way have an important drawback. When a noise spike or an abnormally short pulse occurs in the external chip enable signal XCEB, an unnecessary read/write operation is perform
Hoang Huan
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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