Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-14
2002-07-16
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S267000, C257S298000
Reexamination Certificate
active
06420232
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to flash memory devices and more particularly to very high-density, high-speed and low-power split-gate flash memory devices.
2. Description of Related Art
The flash memory devices are known to store charges in an isolated gate (known as the floating gate) by means of either, Fowler-Nordheim tunneling or hot-carrier injection through a thin insulator layer from the semiconductor substrate and to remove or erase charges stored in an isolated gate by means of Fowler-Nordheim tunneling through a thin insulator layer to the semiconductor substrate or the control gate. Basically, the cell size must be scaled down for high-density mass storage applications and the device structure must be developed toward low-voltage, low-current and high-speed operation with high endurance and high retention.
Based on the device structure, the prior arts can be basically divided into two categories: stack-gate structure and split-gate structure. A typical stack-gate structure of conventional flash memory device is shown in
FIG. 1
, where the device gate length is mainly limited by the minimum feature size of technology used and the device is recognized to be a one-transistor device; a typical split-gate structure of conventional flash memory device is shown in
FIG. 2
, where the device gate length including the floating-gate length and the control-gate length is recognized to be a 1.5 transistor device. The stack-gate flash memory device shown in
FIG. 1
includes a p-type substrate
100
, an n
+
-type source diffusion region
101
and an n
+
-type drain diffusion region
103
inserted in an n-type drain diffusion region
102
. A thin tunneling-oxide layer
104
is provided on the surface of a p-type substrate
100
having a thickness of approximately 100 Angstroms. A polycrystalline-silicon layer
105
acted as the floating gate is provided on a thin tunneling-oxide layer
104
, and an inter-gate dielectric layer
106
using the ONO structure separates the floating gate
105
and the control gate
107
using the polycide layer.
The programming of the stack-gate flash memory device shown in
FIG. 1
is accomplished by applying a relatively high positive voltage to the control gate and a moderately high positive voltage to the source of the device, and the drain is grounded. The device is operated in saturation region and the high lateral electric field across the channel-modulation region near the source is used to generate hot carriers in which hot electrons with energy higher than the interface barrier (~3.15 eV) between the conduction bands of the thin tunneling-oxide layer and the semiconductor substrate are injected into the floating gate and stored there, and the hot holes generated produce the substrate current. Since most of channel carriers are collected by the positive source voltage, the injection efficiency is poor and most of the drain current is wasted. Moreover, the programming power is large, resulting in a further difficulty for high-density mass storage applications.
The erasing of the stack-gate flash memory device shown in
FIG. 1
is accomplished by applying a relatively high positive voltage to the drain while the control gate is grounded and the source is usually floating. The stored electrons in the floating gate are tunneling from the floating gate to the drain by high electric field across the thin tunneling-oxide layer over the double-diffused drain. The above erasing is slightly modified by reducing the applied voltage across the drain and substrate junction while the control gate is applied with a moderately high negative voltage. The reduction of the drain voltage is mainly used to eliminate the band-to-band tunneling effects which may produce hot-hole injection or holes trapped in the gate oxide. Apparently, a deeper double-diffused drain junction is needed to have a larger overlapping area for the thin tunneling-oxide layer and further to eliminate the band-to-band tunneling effects, resulting in lower read speed due to larger gate-drain overlapping capacitance and drain-substrate junction capacitance and a further difficulty for device scaling. Moreover, the erase of stored electrons from the floating gate to the overlapped drain is not self-limiting, resulting in the over-erase problem which needs complicated circuitry and software to perform a series of erase and verify steps.
A typical split-gate flash memory device shown in
FIG. 2
includes a p-type substrate
110
and n
+
-type source and drain diffusion regions
118
,
117
provided in the p-type substrate
110
. A thin tunneling-oxide layer
111
is formed on the surface of a portion of the p-type substrate
110
and a portion of the n
+
-type source diffusion region
118
under the polycrystalline-silicon floating-gate
113
. The floating gate
113
overlaps a portion of the source diffusion region
118
and a portion of the channel. A special shape of polycrystalline-silicon oxide
114
is formed on the polycrystalline-silicon floating-gate
113
using the conventional LOCal-Oxidation of Silicon (LOCOS) technique. A dielectric layer
115
separates the sidewall of the polycrystalline-silicon floating-gate
113
from the control gate
116
, and a portion of the control gate
116
is formed on a thicker gate-oxide layer
112
. The control gate
116
overlaps a portion of the drain diffusion region
117
and a portion of the channel through a thicker gate-oxide layer
112
. Apparently, the limitation of lithographic alignment tolerance of the control gate results in a barrier for further device scaling besides the natural limitation due to 1.5 transistor based on the lithographic point of view. Therefore, the prior art shown in
FIG. 2
is not suitable for high-density mass-storage applications if the cost per bit is concerned. Moreover, a large source-substrate junction capacitance becomes a major limitation for high-speed read operation.
The programming of the conventional split-gate flash memory device shown in
FIG. 2
is accomplished by applying a relatively low positive voltage (threshold voltage of the control-gate transistor) and a relatively high positive voltage to the source of the device, and the drain is grounded. The hot carriers are generated by high lateral electric field under the gap between the floating gate and the control gate. The generated hot-electrons with energy higher than the interface barrier (~3.15 eV) between the conduction bands of the thin gate-oxide and the p-type substrate are injected into the floating gate and stored there, and the hot-holes generated produce the substrate current. Apparently, much larger source voltage is needed because a portion of applied source voltage is dropped across the channel formed under the control gate and the channel under the floating gate, as compared to that of the stack-gate flash memory device. However, the channel current for programming which is controlled by the control gate is much smaller than that of the stack-gate flash memory device shown in FIG.
1
and this is one of the advantages of the split-gate flash memory device.
The erasing of the conventional split-gate flash memory device shown in
FIG. 2
is accomplished by applying a relatively high positive voltage to the control gate while the source and the drain are grounded. The erasing is performed by using Fowler-Nordheim tunneling from the floating gate to the control gate through the sidewall injector along the edge of the floating gate and is self-limiting through the accumulation of positive charges on the injector of the floating gate. Therefore, the over-erase problem doesn't occur for the split-gate flash memory device shown in
FIG. 2
, the erasing circuitry is then much simpler than that of the stack-gate flash memory device shown in FIG.
1
. However, the smiling effect due to the oxidation of the sidewall of the polycrystalline-silicon floating gate may produce the reverse tunneling disturbs. Therefore, a thicker polycrystalline-silicon oxide grown on t
Blum David S
Chaudhari Chandra
Pepper Hamilton LLP
Silicon-Based Technology Corp.
Singer, Esq. James M.
LandOfFree
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