Method for fabricating nonvolatile semiconductor memory device

Details Method for fabricating nonvolatile semiconductor memory device Method for fabricating nonvolatile semiconductor memory device

2000-03-24

2002-04-09

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S297000, C257S316000

Reexamination Certificate

active

06368916

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a single gate-type nonvolatile semiconductor memory device including a charge storage layer formed of a stacked film of silicon oxide film, silicon nitride film and silicon oxide film, and a method for fabricating the same.
As rewritable nonvolatile semiconductor memory devices, semiconductor memory devices, such as EEPROMs, flash EEPROMs, etc., which store information by storing charges in floating gates, are generally known. Such semiconductor memory devices require floating gates for storing information, in addition to control gates which function as word lines, and accordingly two conductor layers are required to form the memory cell transistors.
On the other hand, as a nonvolatile semiconductor memory device which has a simpler structure and is easy to be highly integrated, a nonvolatile semiconductor memory device including the memory cell transistors having single gates is proposed.
A conventional nonvolatile semiconductor device including the single gates will be explained with reference to FIG.
12
.
FIG. 12
is a sectional view of the conventional nonvolatile semiconductor memory device.
A plurality of bit lines
114
of an n
+
diffused layer are formed on a silicon substrate
100
, extended normally to the sheet of the drawing. A bit line oxide film
116
is formed on the bit lines
114
. A pocket layer
112
of a p
−
diffused layer is formed on both sides of the silicon substrate
100
in the regions between the bit lines
114
. Charge storage layer
108
of a stacked film of a silicon oxide film
102
, a silicon nitride film
104
and a silicon oxide film
106
is formed on the silicon substrate
100
between the bit lines
114
. A plurality of word lines
124
are formed on the bit line oxide film
116
and the charge storage layer
108
, extended crossing the bit lines
114
. Thus, the single gate-type memory cell transistors having control gates formed of the word lines
124
are formed.
Then, the method for fabricating the conventional nonvolatile semiconductor memory device shown in
FIG. 12
will be explained with reference to
FIGS. 13A-13D
and
14
A-
14
D.
FIGS. 13A-13D
and
14
A-
14
D are sectional views of the conventional nonvolatile memory device in the steps of the method for fabricating the same, which show the method.
First, an about 200-800 nm-thick device isolation film (not shown) is formed on the silicon substrate
100
by, e.g., the usual LOCOS method to define device regions. The device isolation film is not formed in the memory cell regions.
Next, an about 5-10 nm-thick silicon oxide film
102
is formed on the silicon substrate
100
with the device isolation film formed on by, e.g., thermal oxidation method or CVD method.
Then, an about 2-15 nm-thick silicon nitride film
104
is formed on the silicon oxide film
102
by, e.g., CVD method.
Next, an about 5-10 nm-thick silicon oxide film
106
is formed on the silicon nitride film
104
by, e.g., CVD method.
Thus, the charge storage layer
108
of a stacked structure of the silicon oxide film
102
, the silicon nitride film
104
and the silicon oxide film
106
is formed (FIG.
13
A).
Then, a photoresist film
110
for exposing regions for the bit lines
114
to be formed in is formed on the charge storage film
108
by the usual lithography. The photoresist film
110
has a stripe pattern extended normally to the drawing sheet.
Then, with the photoresist film
110
as a mask, B
+
(boron) ions are implanted to form in the silicon substrate
100
the p
−
diffused layer
112
which is to be the pocket layer (FIG.
13
B). The B
+
ions are implanted, for example, at about 20-40° to a normal to the silicon substrate
100
, at acceleration energy of 50-60 keV, and at a dose of 1.0-3.0×10
13
cm
−2
.
Next, the silicon oxide film
106
and the silicon nitride film
104
are etched by dry etching with the photoresist film
110
as a mask (FIG.
13
C).
Then, As
+
(arsenic) ions are implanted with the photoresist film
110
as a mask to form in the silicon substrate
100
the bit lines
114
which function also as the source/drain diffused layer regions (FIG.
13
D). As
+
ions are implanted, for example, at acceleration energy of 50-60 keV and at a dose of 1.0-3.0×10
15
cm
−3
. In the previous step the silicon oxide film
102
is not removed, and remains. This is for the prevention of contamination of the silicon substrate
100
in this ion implanting step.
Next, the photoresist film
110
is removed by the usual ashing.
Then, the silicon substrate
100
is thermally oxidized to form the bit line oxide film
116
of about 50-100 nm-thick on the bit lines
114
. The silicon substrate
100
in the regions between the bit lines
114
is not oxidized because of the silicon nitride film
104
which functions as an oxidation mask.
Then, an about 5-10 nm-thick silicon oxide film
118
is formed on the silicon substrate
100
by thermal oxidation (FIG.
14
A). The silicon oxide film
118
is a coating film for preventing the silicon nitride film
104
from exposing to thereby deteriorate data retention characteristics.
Next, a conductor film which is to be the word lines is deposited on the entire surface. For example, first an about 100-150 nm-thick polycrystalline silicon film
120
is deposited. Then, P (phosphorus) as an impurity is heavily introduced into the polycrystalline silicon film
120
by, e.g., vapor phase diffusion or ion implantation to make the polycrystalline silicon film
120
less electrical resistance. Then, an about 100-150 nm-thick WSi (tungsten silicide) film
122
is deposited on the polycrystalline silicon film
120
by, e.g., CVD method. Thus, the polycide structure of the stacked film of the WSi film
122
and the polycrystalline silicon film
120
is formed.
Next, the stacked film of the WSi film
122
and the polycrystalline silicon film
120
is patterned by the usual lithography and etching to form the word lines
124
of the stacked film of the WSi film
122
and the polycrystalline silicon film
120
. A plurality of the word lines
124
are extended, crossing the bit lines
114
.
Then, ion implantation is performed with the bit lien oxide film
116
and the word lines
124
as a mask to form a channel cut layer (not shown) for the isolation of the memory cells. The channel cut layer is formed by implanting B
+
ions, for example, at 20-30 keV acceleration energy and at a dose of 1.0-3.0×10
12
cm
−2
.
Next, an about 20-30 nm-thick silicon nitride film, an about 100-150 nm-thick silicon oxide film and an about 600-900 nm-thick BPSG film, etc. are sequentially deposited on the entire surface by, e.g., CVD method to form an inter-layer insulation film
126
of the stacked film of these insulation films.
Then, a required interconnection layer, etc. are formed on the inter-layer insulation film
126
by the usual semiconductor fabrication method.
Thus, the nonvolatile semiconductor memory device including the single gates is fabricated.
However, in the above-described conventional nonvolatile semiconductor memory device, as shown in
FIG. 15A
, the ion implantation for forming the p
−
diffused layer
112
is performed after the charge storage layer
108
has been formed, which often damages the charge storage layer
108
near the drain regions and the charge storage layer
108
near the source regions (see FIG.
15
B). The charge storage layer
108
especially near the source/drain regions (the actual charge storage layer is the silicon nitride film
104
) is a region where electrons are captured to retain information. The damage of the region deteriorates charge retention characteristics, which often leads to deterioration of cycling characteristics and data retention characteristics of the nonvolatile semiconductor memory device.
In the conventional nonvolatile semiconductor memory device, as shown in
FIG. 16A
, the silicon oxide film
106
and the silicon nitride film
104
are etched with the silicon oxide film
102
as

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