Method of forming an NROM embedded with mixed-signal circuits

Details Method of forming an NROM embedded with mixed-signal circuits Method of forming an NROM embedded with mixed-signal circuits

2001-11-02

2002-09-10

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S981000

Reexamination Certificate

active

06448137

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to forming nitride read only memory (NROM), and more particularly, to a method of forming an NROM embedded with mixed-signal circuits.
2. Description of the Prior Art
Nitride read only memory (NROM) is a semiconductor device for data storage. It is composed of a plurality of memory cells. Each of the memory cells comprises a MOS transistor and an ONO gate dielectric layer. Since the silicon nitride layer in the ONO gate dielectric layer is a highly dense material, hot electrons can be trapped in the silicon nitride layer by way of tunneling through the MOS transistor, in order to store data. Although NROM has an advantage of a two bit multi-storage function, a simpler manufacturing process than similar products, such as flash ROM, and being widely welcomed by the market, it is not good enough to just make conventional improvements. Because, the semiconductor industry is orienting itself toward the development of system on chip (SOC) products, in other words, products in which are simultaneously manufactured memory devices and the circuits devices, so as to make a single chip comprise memory and mixed-signal circuits. In U.S. Pat. No. #5,908,311, a method of forming a mixed-signal circuits comprising the flash ROM is proposed. Based on different characteristics and applications of NROM and flash ROM, it is a very important issue to develop a system on chip which integrates NROM and mixed-signal circuits.
Please refer to
FIG. 1
to FIG.
10
.
FIG. 1
to
FIG. 10
are schematic diagrams of a process for making the mixed-signal circuits comprising flash ROM. As shown in
FIG. 1
, the mixed-signal circuits comprising flash ROM according to the prior art are made on a surface of a semiconductor substrate
10
. The semiconductor substrate
10
comprises a P
+
substrate
12
, and a P
−
epi layer
14
. The surface of the semiconductor substrate
10
comprises a memory area
11
and a periphery area
13
. The periphery area
13
further comprises a 3-volt transistor area
15
and a 5-volt transistor area
17
. An N-well region
16
of MOS, a P-well region (not shown) of MOS, a channel stop implant
18
, and at least a field oxide region (FOX)
22
are in the periphery area
13
. A P-well region
23
is in the memory area.
The prior art method is to form a sacrificial oxide layer
24
on the surface of the semiconductor substrate
10
first, then perform a first photolithography process and form a first mask
25
in order to expose the 5-volt transistor region
17
in the N-well region
16
. Thereafter, perform a first ion implantation process in order to adjust the threshold voltage of the 5-volt transistor (not shown) in the N-well region
16
. After that, perform a second photolithography process and a second ion implantation process in order to adjust the threshold voltage of the 5-volt transistor (not shown) in the P-well region (not shown).
As shown in
FIG. 2
, after adjusting the threshold voltage of the 5-volt transistor (not shown), the sacrificial oxide layer
24
is removed completely. Then form a sacrificial oxide layer
28
on the surface of the semiconductor substrate
10
. Thereafter, perform a third photolithography process to expose the memory region
11
by utilizing a third mask
32
. Then perform a third ion implantation process in order to adjust the threshold voltage of the memory cell (not shown).
As shown in
FIG. 3
, after adjusting the threshold voltage of the memory cell (not shown), remove the sacrificial oxide layer
28
in the memory area
11
, then remove the third mask
32
. After that form a sacrificial oxide layer
34
in the memory area
11
. The formation of the sacrificial oxide layer
34
will contribute to a thickness increase of the sacrificial oxide layer
28
in the periphery region
13
. However, the growth rate of the sacrificial oxide layer
34
is obviously larger than that of the sacrificial oxide layer
28
in this process step.
As shown in
FIG. 4
, form a first polysilicon layer
36
on the surface of the sacrificial oxide layer
28
, the sacrificial oxide layer
34
and the field oxide layer
22
, then perform a fourth photolithography process and form a fourth mask
37
. The fourth mask
37
exposes the predetermined site
39
of the resistor in the periphery area
13
and the memory area
11
. Thereafter, perform a fourth ion implantation process in order to dope the predetermined site
39
of the resistor in the periphery area
13
and the memory area
11
with low doping. After that remove the fourth mask
37
. Then perform a fifth photolithography process (not shown) and a fifth ion implantation process (not shown) in order to dope the region outside of the predetermined site
39
of the resistor in the periphery area
13
and the memory area
11
with high doping.
As shown in
FIG. 5
, perform a sixth photolithography process in order to form a sixth mask
41
. The sixth mask
41
exposes the 3-volt transistor region
15
and defines the resistor
38
, the bottom electrode
42
of the capacitor, the gate
44
of the 5-volt transistor (not shown) and the floating gate
46
of the flash ROM cell (not shown). Then, perform a first etching process in order to remove the first polysilicon layer
36
not covered by the sixth mask
41
and form at least a resistor
38
, a bottom electrode
42
of the capacitor, a gate
44
of the 5-volt transistor (not shown) and the floating gate
46
of the flash ROM cell (not shown) on the semiconductor substrate
10
. Thereafter, remove the sixth mask
41
.
As shown in
FIG. 6
, form a bottom oxide-nitridetop oxide(ONO)
48
structure on the semiconductor substrate
10
that covers the resistor
38
, the bottom electrode
42
of the capacitor, the gate
44
of the 5-volt transistor(not shown), the floating gate
46
of the flash ROM cell(not shown), the exposed field oxide layer
22
and the gate oxide layer
28
in the 3-volt transistor region
15
. Then, perform a seventh photolithography process in order to form a seventh mask
49
. The seventh mask
49
exposes the 3-volt transistor region
15
. Thereafter, perform a second etching process in order to remove portions of the ONO layer
48
not covered by the seventh mask
49
. After that, remove the seventh mask
49
.
Please refer to FIG.
7
. Perform an eighth photolithography process in order to form an eighth mask
52
on the surface of the ONO layer
48
. The eighth mask
52
exposes the 3-volt transistor region
15
in the N-well region
16
. Thereafter, perform a sixth ion implantation process in order to adjust the threshold voltage of the 3-volt transistor (not shown) in the N-well region
16
. After that, perform a third etching process in order to remove the gate oxide layer
28
in the 3-volt transistor region
15
, then remove the eighth mask
52
. Thereafter, form a gate oxide layer
54
atop the 3-volt transistor region
15
. After that, perform a ninth photolithography process and a seventh ion implantation process in order to adjust the threshold voltage of the 3-volt transistor (not shown) in the P-well region. Since the manufacturing of the 5-volt transistor (not shown), the resistor
38
, the capacitor
54
and the flash ROM cell (not shown) occurs earlier than the manufacturing of the 3-volt transistor (not shown), the effect on the 3-volt transistor (not shown) resulting from improper heat treatment is avoided.
As shown in
FIG. 8
, form a second polysiliocn layer
56
on the semiconductor substrate
10
that covers the gate oxide layer
54
, the exposed field oxide layer
22
and the ONO layer
48
. Then, perform a doping process to the second polysiliocn layer
56
. Thereafter, as shown in
FIG. 9
, perform a tenth photolithography process in order to form a ninth mask
57
on the surface of the second polysilicon layer
56
. The ninth mask
57
defines the gate
58
of the 3-volt transistor (not shown), the top electrode
62
of the capacitor
64
and the control gate (not shown) of the flash ROM cell (not shown). After that, p

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