Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-02-25
2002-04-16
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000
Reexamination Certificate
active
06373095
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to nonvolatile memories that use a floating gate transistor as a single bit memory device. Specifically, an NVRAM memory cell is described having increased coupling between the floating gate and control gate without a significant increase in cell area.
Nonvolatile memories are used in digital computing devices for the storage of data. The nonvolatile memory is typically a semiconductor memory comprising thousands of individual transistors configured on a substrate to form a matrix of rows and columns of memory cells. The semiconductor memories have relatively fast access times and provide a high data storage density. The physical size of the nonvolatile memory arrays limits the data storage capacity for the memory.
In one type of nonvolatile memory, floating gate transistors are used as the memory device. The potential on the control gate is coupled to the floating gate to program the charge stored on the floating gate. The devices are programmed by injecting a charge onto the floating gate dielectric by means of tunneling or hot electron injection. The presence or absence of stored charge determines a conduction state for the transistor which in turn represents a logic state. The floating gate transistors are used to implement erasable programmable read only memories where the injected charge is nonvolatily stored for long periods of time even after the power has been turned off to the memory. Erasure of the data is effected by a potential which is applied to a control gate of the floating gate transistor.
In the conventional architecture of E-PROM cell arrays, each column of floating gate transistors have the drain contacts of the transistors connected together, and the transistors of each column have their control gate lines connected together. The sources of floating gate transistors in the same column are electrically connected in common, and are also connected to an adjacent column for a flash type architecture. The individual transistors of the matrix are formed in a common silicon substrate, and transistors arranged in the same row are separated by a field isolation structure from transistors in a subsequent row.
The coupling between the control gate and floating gate is proportional to the amount of common area separating the floating gate from the control gate. In a conventional CMOS NVRAM cell structure, the floating gate is extended over a thick oxide dielectric to increase the coupling ratio of the control gate to the floating gate. The thickness of the oxide is optimized for reliability and a minimization of defects, as well as for optimum coupling. These objectives directly control the cell area, thereby affecting the storage density of the memory array. Thus, in order to increase the storage density and obtain the corresponding increase in data density per unit area, it is desirable to increase the coupling ratio of the floating gate to the control gate of an individual cell transistor, without increasing the corresponding size of the transistor.
Attempts at increasing the coupling between the control gate and floating gate of an NVRAM cell are disclosed in U.S. Pat. Nos. 5,315,142 and 5,380,672. The memory cells of these devices are formed in a three-dimensional trench structure in the silicon substrate, and have a floating gate structure which is coupled to a control gate over essentially three surfaces. Placing the floating gate within the trench provides an opportunity to locate a control gate along the inside vertical upstanding walls of the floating gate, as well as the portion of the floating gate which resides in the bottom of the trench. The floating gate is charged and discharged due to tunneling of electrons in the vertical sidewalls which incorporate source and drain regions, and the floating gate. The trench memory cell structures occupy only a small amount of surface area while maintaining a high coupling ratio between the control gate and the floating gate.
The present invention represents a further attempt to increase coupling between the control gate and the floating gate without the use of trench architecture, and without a significant increase in cell area.
SUMMARY OF THE INVENTION
It is an object of this invention to increase the coupling ratio between a control gate and floating gate of an NVRAM memory cell.
It is a further object of this invention to increase the coupling ratio between a control gate and floating gate of a transistor without increasing the cell area.
These and other objects of the invention are provided for by a transistor, and a method for manufacturing the same, in accordance with the invention. The invention provides an NVRAM cell having a floating gate which is disposed over a channel extending between a source and drain region of a thin film field effect transistor. The floating gate is insulated from the source and drain regions by a tunneling oxide, and is U-shaped having two vertically extending sidewalls. A second insulation layer, such as oxide nitride oxide (ONO) layer is disposed within the U-shaped interior of the floating gate, and over the top and exterior surface of the vertically extending sides. A second layer of polysilicon forms a control gate for all of the cells in the same column. The second polysilicon layer conforms to the floating gate interior over the oxide nitride oxide layer and over the top and exterior surfaces of the insulated sidewalls.
The exterior surface of the vertical sidewalls of the floating gate structure, as well as the interior surface of the floating gate are capacitively coupled to the control gate through the ONO layer. The total surface area between control gate and floating gate is increased by virtue of the outside surface area of the vertically extending sidewalls of the floating gate and the interior vertical sidewalls of the control gate, thereby increasing the coupling ratio without suffering an increase in substrate surface area for the device.
REFERENCES:
patent: 4703456 (1987-10-01), Arakawa
patent: 4757360 (1988-07-01), Faraone
patent: 5089867 (1992-02-01), Lee
patent: 5111270 (1992-05-01), Tzeng
patent: 5315142 (1994-05-01), Acovic et al.
patent: 5345417 (1994-09-01), Crotti
patent: 5380672 (1995-01-01), Yuan et al.
patent: 5382540 (1995-01-01), Sharma et al.
patent: 5465249 (1995-11-01), Cooper, Jr. et al.
patent: 5523970 (1996-06-01), Riggio, Jr.
patent: 5563083 (1996-10-01), Pein
patent: 5677216 (1997-10-01), Tseng
patent: 5877980 (1999-03-01), Mang et al.
patent: 5915177 (1999-06-01), Tseng
patent: 63-131582 (1988-06-01), None
patent: 03-034578 (1991-02-01), None
patent: 03034581 (1991-02-01), None
patent: 11074380 (1999-03-01), None
Bracchitta John A.
Nakos James S.
Chadurjian Mark
Connolly Bove & Lodge & Hutz LLP
Hu Shouxiang
Thomas Tom
LandOfFree
NVRAM cell having increased coupling ratio between a control... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with NVRAM cell having increased coupling ratio between a control..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and NVRAM cell having increased coupling ratio between a control... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2898280