Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-04-09
2002-06-04
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S648000
Reexamination Certificate
active
06399438
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and the art of manufacturing the same; and, more specifically, the invention relates to improvements applicable to a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).
The memory cells of a DRAM are arranged at the cross points of a plurality of word lines and a plurality of bit lines all of which are arranged in a matrix over the principal surface of the semiconductor substrate, and each of the memory cells includes one memory cell selecting MISFET and one information storing capacitive element (capacitor) which is connected in series with the memory cell selecting MISFET. The memory cell selecting MISFET mainly includes a gate oxide film, a gate electrode formed integrally with a word line, and a pair of semiconductor regions which constitute a source and a drain. The bit line is arranged above the memory cell selecting MISFET, and is electrically connected to either one of the source and the drain. The information storing capacitive element is similarly arranged above the memory cell selecting MISFET, and is electrically connected to the other of the source and the drain.
As described above, recent types of DRAMs have adopted a so-called stacked capacitor structure in which information storing capacitive elements are arranged above memory cell selecting MISFETs to compensate for a decrease in the charge storage quantity per information storing capacitive element due to the scaling of memory cells. DRAMs which adopt this stacked capacitor structure are divided into two kinds, a capacitor under bitline (CUB) structure in which information storing capacitive elements are arranged below bit lines and a capacitor over bitline (COB) structure in which information storing capacitive elements are arranged above bit lines.
In the above-described two kinds of stacked capacitor structures, as compared with the CUB structure, the COB structure in which information storing capacitive elements are arranged above bit lines is suited to scaling of memory cells. This is because if the charge storage quantity of a scaled information storing capacitive element is to be increased, it is necessary to three-dimensionally design the structure of the information storing capacitive element and increase the surface area thereof, but in the case of the CUB structure in which bit lines are arranged above information storing capacitive elements, contact holes for connecting the bit lines and the memory cell selecting MISFETs become extremely large in aspect ratio and the contact holes become difficult to open.
In the case of recent large-capacity DRAMs such as 64- or 256-Mbit DRAMs, it has become difficult to ensure the required charge storage quantity merely by three-dimensionally forming information storing capacitive elements and increasing the surface areas thereof, and in addition to the three-dimensional formation of the capacitive elements, consideration has been given to the use of a capacitive insulating film formed of a high dielectric material such as Ta
2
O
5
(tantalum oxide), (Ba, Sr)TiO
3
(barium strontium titanate; hereinafter referred to as BST) or SrTiO
3
(strontium titanate; hereinafter referred to as STO). DRAMs using a capacitive insulating film formed of such a high dielectric material are described in, for example, Japanese Patent Laid-Open No. 222469/1989 and U.S. Pat. No. 5,383,088.
Furthermore, in the field of the above-noted 64- to -256-Mbit DRAMs, it is considered that it becomes inevitable to use a metal material which is lower in resistance than polycrystalline silicon film, for the material of word lines and bit lines as a countermeasure for signal delay due to an increase in chip size or to use the silicidation technique of forming a high melting-point metal silicide layer such as TiSi
2
(titanium silicide) or CoSi
2
(cobalt silicide) over the surfaces of the sources and drains of MISFETs which constitute peripheral circuits such as sense amplifiers and word drivers which are required to perform high-speed operation, as a countermeasure for avoiding an increase in resistance due to the scaling of contact holes for connecting interconnect lines and the sources and drains of the MISFETs. This silicidation technique is described in, for example, Japanese Patent Laid-Open Nos. 29240/1994 and 181212/1996.
SUMMARY OF THE INVENTION
In DRAMs which belong to a 256-Mbit or later generation, as a countermeasure for signal delay due to an increase in chip size, the gate electrodes (word lines) of memory cell selecting MISFETs and the gate electrodes of MISFETs of peripheral circuits are formed of a low-resistance material mainly made of a high melting-point metal such as W (tungsten), and as a countermeasure for decreasing the contact resistance between diffusion layers and interconnect lines, a high melting-point silicide layer is formed over the surfaces of the sources and drains of the MISFETs which constitute the peripheral circuits.
In such DRAMs, as a countermeasure for the signal delay of bit lines, the bit lines are formed of a low-resistance material mainly made of a high melting-point metal such as W, and as a countermeasure for reducing the number of process steps for forming the interconnect lines, the bit lines and first-layer interconnect lines of the peripheral circuits are formed at the same time in one process step. Moreover, in the DRAMs, as a countermeasure for ensuring the charge storage quantities of the information storing capacitive elements, a COB structure in which information storing capacitive elements are arranged above bit line is adopted to facilitate the three-dimensional formation of the capacitive elements, and capacitive insulating films are formed of a high dielectric material such as Ta
2
O
5
(tantalum oxide).
However, the present inventor examined the above-described DRAM manufacturing process, and found out a phenomenon in which the bit lines formed above the MISFETs and the first-layer interconnect lines of the peripheral circuits peeled off the surfaces of the insulating films during high-temperature heat treatment which was performed in a subsequent process step for forming the information storing capacitive elements.
The outline of a process for manufacturing the above-described type of DRAM will be described in brief below. First of all, a low-resistance material which is mainly made of a high melting-point metal deposited over a principal surface of a semiconductor substrate is patterned to form gate electrodes (word lines) of memory cell selecting MISFETs and gate electrodes of MISFETs of a peripheral circuit, and then an impurity is ion-implanted into the semiconductor substrate to form the sources and drains of these MISFETs.
Then, after these MISFETs are covered with an insulating film, contact holes are formed in the insulating film above the respective sources and drains of the memory cell selecting MISFETs, and polycrystalline silicon plugs are buried into the respective contact holes. Then, after contact holes are formed in the insulating film above the respective gate electrodes, sources and drains of the MISFETs of the peripheral circuit, a high melting-point metal film such as a Ti film or a Co film is thinly deposited over the insulating film as well as the interiors of these contact holes. Then, the semiconductor substrate is heat-treated to cause the substrate (Si) and the high melting-point metal to react with each other at the bottoms of the contact holes, thereby forming a high melting-point metal silicide layer at the bottoms of the contact holes.
Then, after an interconnect-line material which mainly contains a high melting-point metal such as W is deposited over the insulating film as well as the interiors of the contact holes of the peripheral circuit, the interconnect-line material and an unreacted Ti film remaining on the surface of the insulating film are patterned to form bit lines and first-layer interconnect lines of the peripheral circuit over the insulating film. The bi
Aoki Hideo
Asano Isamu
Fukuda Naoki
Fukuda Takuya
Goto Hidekazu
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Tsai Jey
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