Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
1999-04-28
2002-05-28
Kim, Kenneth S. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
C710S071000, C710S260000, C710S268000, C710S005000, C710S039000, C712S200000, C712S038000
Reexamination Certificate
active
06397325
ABSTRACT:
The invention relates to a microcomputer and computer system including a method of operating the same.
BACKGROUND OF THE INVENTION
Computer systems may incorporate a processor with a plurality of other devices which may generate signals for transmission between each other on-chip and between chips. When transmitting interrupt signals between devices on-chip the source and destinations may be numerous thereby requiring complex interconnections or control systems. Problems can arise in transmitting such signals between chips due to the limited number of pins available for external connections.
It is an object of the present invention to provide an improved computer system and method of operating a computer system in which a plurality of signals including interrupt signals may be transmitted between devices on-chip and off-chip while avoiding the need for excessive numbers of pins or wires.
SUMMARY OF THE INVENTION
The invention provides a computer system comprising an integrated circuit device having an address and data path interconnecting a plurality of on-chip devices including at least one CPU, at least one other module and an external communication port, said CPU being arranged to generate event request packets and memory access packets, said module having circuitry responsive to an event to generate event request packets, each of said event and memory access packets including a destination address and being distributed in parallel format on said address and data path, the external communication port including circuitry to reduce the parallel format of each packet to a more serial format for off-chip communication.
Preferably said CPU and at least one other module includes packet generating circuitry operable in response to receipt of a request packet to generate a response packet for distribution on said address and data path.
Preferably said packet generating circuitry is arranged to provide in each request packet an indication of the source of the packet as well as the destination, said source address being used as a destination address in each response packet.
Preferably said address and data path comprises one or more buses arranged for distribution of request and response packets in bit parallel format.
Preferably a memory interface is provided on-chip communicating with said address and data path to permit memory read and write operations.
Preferably the external communication port on each chip includes bit format translation circuitry for translating on-chip bit parallel format to off-chip bit serial format.
Preferably said at least one other module includes packet generating circuitry to generate event request packets of two types, the first type forming an interrupt request and a second type providing control commands.
Preferably said integrated circuit device comprises an on-chip memory accessible by addressed memory access packets on said address and data path.
The on-chip memory interface may be connected to an off-chip memory.
The invention includes a method of operating a computer system comprising an integrated circuit device having an address and data path interconnecting a plurality of on-chip devices including at least one CPU, at least one other module and an external communication port, which method comprises distributing on said address and data path event request packets generated by packet generating circuitry in said at least one module and distributing event request packets and memory access packets generated by packet generating circuitry of said CPU, said event and memory access packets being distributed in parallel format on said address and data path and the external communication port being operated to reduce the parallel format of each packet to a more serial format for off-chip communication.
Preferably packet generating circuitry of said CPU is operable in response to receipt of a request packet to generate a response packet for distribution on said address and data path.
Preferably each request packet includes an indication of the source of the packet as well as the destination, said source address being used as a destination address in each response packet.
Preferably memory access operations are effective with an on-chip memory through a memory interface provided on-chip and communicating with said address and data path.
An off-chip memory may be connected to an external memory interface on the chip, and memory access operations being effected by memory access packets on the address and data path addressing said external memory interface.
Communication through the external memory interface may remain in bit parallel format.
Preferably said event request packets include packets of two types, a first type forming an interrupt request and a second type providing control commands.
REFERENCES:
patent: 5283904 (1994-02-01), Carson et al.
patent: 5495615 (1996-02-01), Nizar et al.
patent: 6125416 (2000-09-01), Warren
patent: 0 644 489 (1995-03-01), None
patent: WO 95/16965 (1995-06-01), None
Jones Andrew Michael
May Michael David
Carlson David V.
Jorgenson Lisa K.
Kim Kenneth S.
Seed IP Law Group PLLC
STMicroelectronics Limited
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