Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-30
2002-09-03
Wojciechowicz, Edward (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S299000, C257S316000, C257S321000
Reexamination Certificate
active
06445030
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to processing a non-volatile semiconductor memory device and non-volatile semiconductor memory devices having improved erase speed. In particular, the present invention relates to forming a memory device with a tunnel oxide containing fluorine to improve erase speed.
BACKGROUND ART
Semiconductor devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art
FIG. 1
, a memory device such as a flash memory
10
comprises one or more high density core regions
11
and a low density peripheral portion
12
on a single substrate
13
. The high density core regions
11
typically consist of at least one M×N array of individually addressable, substantially identical floating-gate type memory cells and the low density peripheral portion
12
typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion
11
are coupled together in a NAND-type circuit configuration, such as, for example, the configuration illustrated in prior art FIG.
2
. Each memory cell
14
has a drain
14
a
, a source
14
b
and a stacked gate
14
c
. A plurality of memory cells
14
connected together in series with a drain select transistor at one end and a source select transistor at the other end to form a NAND string as illustrated in prior art FIG.
2
. Each stacked gate
14
c
is coupled to a word line (WL
0
, WL
1
, . . . , WLn) while each drain of the drain select transistors are coupled to a bit line (BL
0
, BL
1
, . . . , BLn). Lastly, each source of the source select transistors are coupled to a common source line Vss. Using peripheral decoder and control circuitry, each memory cell
14
can be addressed for programming, reading or erasing functions.
Prior art
FIG. 3
represents a fragmentary cross section diagram of a typical memory cell
14
in the core region
11
of prior art
FIGS. 1 and 2
. Such a cell
14
typically includes the source
14
b
, the drain
14
a
and a channel
15
in a substrate or P-well
16
; and the stacked gate structure
14
c
overlying the channel
15
. The stacked gate
14
c
further includes a thin gate dielectric layer
17
a
(commonly referred to as the tunnel oxide) formed on the surface of the P-well
16
. The stacked gate
14
c
also includes a polysilicon floating gate
17
b
which overlies the tunnel oxide
17
a
and an interpoly dielectric layer
17
c
overlies the floating gate
17
b
. The interpoly dielectric layer
17
c
is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate
17
d
overlies the interpoly dielectric layer
17
c
. The control gates
17
d
of the respective cells
14
that are formed in a lateral row share a common word line (WL) associated with the row of cells (see, for example, prior art FIG.
2
). In addition, as highlighted above, the drain regions
14
a
of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel
15
of the cell
14
conducts current between the source
14
b
and the drain
14
a
in accordance with an electric field developed in the channel
15
by the stacked gate structure
14
c.
The select transistors have a stacked gated structure similar to the memory cells, except that the first polysilicon layer (floating gate) and the second polysilicon layers (control gate) are shorted together to form a single gate type structure. Select gates typically ensure the selectivity of a particular bit line and prevent the memory cells from passing current during the program operation.
Generally speaking, a flash memory cell is programmed by inducing hot electron injection from a portion of the substrate, such as the channel section near the drain region, to the floating gate. Electron injection carries negative charge into the floating gate. The injection mechanism can be induced by grounding the source region and a bulk portion of the substrate and applying a relatively high positive voltage to the control electrode to create an electron attracting field and applying a positive voltage of moderate magnitude to the drain region in order to generate “hot” (high energy) electrons. After sufficient negative charge accumulates on the floating. gate, the negative potential of the floating gate raises the threshold voltage (V
th
) of its field effect transistor (FET) and inhibits current flow through the channel region through a subsequent “read” mode. The magnitude of the read current is used to determine whether or not a flash memory cell is programmed. The act of discharging the floating gate of a flash memory cell is called the erase function. The erase function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source region of the transistor (source erase or negative gate erase) or between the floating gate and the substrate (channel erase). A source erase operation may be induced by applying a high positive voltage to the source region and a 0 V to the control gate and the substrate while floating the drain of the respective memory cell.
Referring still to
FIG. 3
, conventional source erase operations for the flash memory cell
14
operate in the following manner. The memory cell
14
is programmed by applying a relatively high voltage V
G
to the control gate
20
and a moderately high voltage V
D
to the drain region
14
a
in order to produce “hot” electrons in the channel region
15
near the drain region
14
a
. The hot electrons accelerate across the tunnel oxide
17
and into the floating gate
18
and become trapped in the floating gate
18
since the floating gate
18
is surrounded by insulators (the interpoly dielectric
19
and the tunnel oxide
17
). As a result of the trapped electrons, the threshold voltage of the memory cell
14
increases. This change in the threshold voltage (and thereby the channel conductance) of the memory cell
14
created by the trapped electrons causes the cell to be programmed.
To read the flash memory cell
14
, a predetermined voltage V
G
that is greater than the threshold voltage of an unprogrammed cell, but less than the threshold voltage of a programmed cell, is applied to the control gate
20
. If the memory cell
14
conducts, then the memory cell
14
has not been programmed (the cell
14
is therefore at a first logic state, e.g., a zero “0”). Likewise, if the memory cell
14
does not conduct, then the memory cell
14
has been programmed (the cell
14
is therefore at a second logic state, e.g., a one “1”). Consequently, it is possible to read each cell
14
to determine whether or not it has been programmed (and therefore identify its logic state).
In order to erase the flash memory cell
14
, a relatively high voltage V
S
is applied to the source region
14
b
and a lower voltage or ground is applied to the control gate
20
, while the drain region
14
a
is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide
17
between the floating gate
18
and the source region
14
b
. The electrons that are trapped in the floating gate
18
flow toward and cluster at the portion of the floating gate
18
overlying the source region
14
b
and are extracted from the floating gate
18
and into the source region
14
b
by way of Fowler-Nordheim tunneling through the tunnel oxide
17
. Consequently, as the electrons are removed from the floating gate
18
, the memory cell
14
is erased.
One aspect of a non-volatile memory cell is erase speed. It is desirable for non-volatile memory cells to exhibit not only consistent but also fast erase times
Ng Che-Hoo
Shiraiwa Hidehiko
Wu Yider
Yang Jean Y.
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Wojciechowicz Edward
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