ESD protection circuit for different power supplies

Details ESD protection circuit for different power supplies ESD protection circuit for different power supplies

2001-06-18

2002-07-30

Huynh, Kim (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000, C257S355000, C257S357000

Reexamination Certificate

active

06426855

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to circuits an integrated circuit that provide protection from electrostatic discharge (ESD) events. More particularly, this invention relates to circuits that will prevent a differential voltage level between two different power supply voltage terminals from exceeding a specified voltage level and thus prevent damage to the integrated circuit.
2. Description of the Related Art
Application specific integrated circuits (ASIC) often have either multiple pads connected to a single power supply voltage source or multiple isolated power supply voltage sources.
FIG. 1
shows a model power supply distribution system similar to that described in “Designing On-Chip Power Supply Coupling Diodes for ESD Protection and Noise Immunity,” S. Dabral et al., Proceedings of EOS/ESD Symposium, 1993, pp. 5B.6.1-5B.6.11.
A power supply voltage source is connected through a distribution system between the Vcc pads
100
and
102
and the Vss pads
120
and
122
. The structure of the ASIC shows a core logic section
110
and a peripheral logic section
138
. In order to isolate noise, such as caused by simultaneous switching of driver circuits in the peripheral logic section
138
or impedance mismatch on transmission line connected to the I/O pad
136
, the peripheral logic section
138
has a separate power supply distribution network from that of the core logic section
110
.
The distribution of the power supply voltage Vcc through the Vcc pad
100
is modeled by the resistor RVcc1
104
the inductor LVcc1
106
. The resistor RVcc1
104
represents the cumulative resistance of the wiring within the ASIC used to distribute the power supply voltage Vcc to the core logic section
110
. The inductor LVcc
106
represents the inductance of the cumulate wiring within the ASIC used to distribute the power supply voltage Vcc to the core logic section
110
.
The return of the power supply voltage Vss through the Vss pad
120
is modeled by the resistor RVss1
116
and the inductor LVss1
118
. The resistor LVss1
116
and the inductor LVss1
118
represent respectively the distributed resistance and inductance of the wiring used to distribute the return of the power supply voltage Vss from the core logic section
110
. The return of the power supply voltage Vss is often a common or ground reference point with the system containing the ASIC.
The capacitance Ccore
112
represents the capacitance of the circuitry of the core logic section
110
between the first power supply voltage node Vcc1
108
and the first return node Vss1
114
of the power supply voltage.
A similar structure is present at the peripheral logic section
138
. The resistor RVcc2
132
and the inductor LVcc2
134
model the distribution wiring from the Vcc pad
106
and the peripheral logic section
138
. The resistor RVss2
146
and the inductor LVss2
148
model the distribution wiring of the return of the power supply Vss from the peripheral logic section
138
and the Vss pad
122
.
The capacitor Cperi represents the capacitance of the circuitry of the peripheral logic section
138
between the second power supply node Vcc2
136
and the second return node Vss 2
142
of the power supply voltage.
The first and second return nodes are generally connected to the semiconductor substrate on which the ASIC is constructed. However, the core logic section and the peripheral logic section may be constructed in a well having a doping of an impurity of a polarity opposite of the doping of the impurity of the semiconductor substrate. This would be an n-well on a p-type substrate or a p-well on an n-type substrate. This will further isolate the return nodes Vss1
114
and Vss2
142
from each other.
While the core logic section
110
and the peripheral logic section
138
were described above as having a common power supply voltage source Vcc, often the core logic section
110
has a power supply voltage source of a different voltage level than the peripheral logic section
138
. The peripheral logic section may have a power supply voltage source Vcc of 5.0V and the core logic section may have a power supply voltage source Vcc of 3.3V. Further, ASIC implementations may have multiple core logic sections and multiple peripheral logic sections, as well as analog core sections. Each section will have a separate voltage distribution network for the power source and return paths. The models for these voltage distribution networks is as described above.
An ESD event is commonly a pulse of a very high voltage typically of several kilovolts with a moderate current of a few amperes for a short period, typically about 100 nanoseconds. The common sources of an ESD event is bringing the ASIC in contact with a human body or a machine such as an integrated circuit tester and handler.
If the I/O pad
140
is contacted and subjected to an ESD event, the second power supply node Vcc2
136
and the second return node Vss2 will begin to change relative to the voltage level of the power supply voltage source Vcc. This change can cause damage in subcircuits that form an interface between the core logic section
110
and the peripheral logic section
138
. “Novel Clamp Circuits for IC Power Supply Protection,” Maloney et al., Proceedings EOS/ESD Symposium, 1995, pp. 1.1.1-1.1.12, Dabral et al., and U.S. Pat. No. 5,616,943 (Nguyen et al.) describe implementations clamp circuits
124
and
130
. The clamp circuits prevent a differential voltage developed between the first power supply node Vcc1
108
and the second power supply node Vcc2
136
or from the first return node Vss 1
114
and the second return node Vss 2
142
from exceeding a clamp voltage. The clamp voltage is larger than the maximum allowable voltage difference between the first power supply node Vcc1
136
and the second power supply node Vcc2
136
, but less than a breakdown voltage that causes damage to the subcircuits that create the interface between the core logic section
110
and peripheral logic circuit
138
.
FIG. 2
shows a schematic of the clamp circuits
124
and
130
of Dabral et al., Maloney et al., and Nguyen et al. The clamp circuit
124
and
130
is connected between a first power supply terminal Vx1
200
and a second power supply terminal Vx2
205
. The diodes D11
210
, D12
215
, . . . D1m
220
are serially connected together, cathode to anode to form a diode chain. The cathode of the first diode D11
210
is connected to the first power supply node Vx1
200
. The anode of the first diode D11
210
is connected to the cathode of the next subsequent diode D12
215
. The anode of the last diode D1m
220
is connected to the second power supply node Vx2
205
, while its cathode is connected to the anode of the next subsequent diode.
The diode chain D21
235
, D22
230
, . . . , D2m
225
are similarly connected between the second power supply node Vx2
205
and the first power supply node Vx1
220
. The cathode of the first diode D21
235
is connected to the second power supply node Vx2
205
, and the anode of the last diode D2m
225
is connected to the first power supply node Vx1
200
.
If the voltage at the power supply node Vx2
205
rises above the total voltage required for the diode chain D11
210
, D12
215
, . . . , D1m
220
to conduct relative to the voltage Vx1
200
, the diode chain D11
210
, D12
215
, . . . , D1m
220
will conduct, clamping the voltage between the second power supply node
205
and the first power supply node
210
to the voltage level across the diode chain D11
210
, D12
215
, . . . , D1m
220
.
Conversely, if the voltage at the power supply node Vx1
200
rises above the total voltage required for the diode chain D21
235
, D22
230
, . . . , D2m
225
to conduct relative to the voltage Vx2
205
, the diode chain D21
235
, D22
230
, . . . , D2m
225
will conduct, clamping the voltage between the first power supply node Vx1
200
and the second power supply node
205
to the voltage level across the diode chain D21
235
, D22
230
, . . . , D2m
225
.
The clampin

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