Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-09-03
2002-07-09
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S565000, C438S592000, C438S657000
Reexamination Certificate
active
06417099
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention provides a method for processing a doped polysilicon layer on a semiconductor wafer, and more particularly, to a method for manufacturing a doped polysilicon layer and controlling the dopant diffusion around the doped polysilicon layer.
2. Description of the Prior Art
In present semiconductor device manufacturing, DRAM (dynamic random access memory) is formed by groups of single transistor DRAM cells and each single transistor DRAM cell comprises a MOS (metal oxide semiconductor) transistor and a capacitor. Please refer to FIG.
1
.
FIG. 1
is a sketching diagram of a normal single transistor DRAM cell. The single transistor cell
10
comprises a P-type Si substrate
12
, an NMOS transistor
14
, a bit line
16
for transferring data, a word line
18
for connecting with other DRAM cells, and a capacitor
20
used for recalling data through the use of storage of charge. The NMOS transistor
14
further comprises a P
+
(phosphorus ion) doped source
22
and drain
24
, and a gate
28
comprising a gate oxide
26
and polycide
27
. The capacitor
20
is made of doped polysilicon with a complex, multi-level 3-D structure, comprises a field plate
21
and a storage node
19
, and is in electrical contact with the drain
24
of the transistor
14
through its storage node
19
.
The source
22
, drain
24
and gate
28
of the NMOS transistor
14
are separately connected with the bit line
16
, capacitor
20
and word line
18
. Using the voltage signal of the word line
18
, the gate
28
can function in determining whether the channel between the bit line
16
and the storage node
19
of the capacitor
20
can become a conducting region by controlling the switching of the channel between the source
22
and drain
24
. It can also retrieve the read and write data within the DRAM cell
10
by storing the current of the bit line
16
into the capacitor
20
or feeding the faradic charges stored in the capacitor
20
back to the bit line
16
. The bit of the DRAM cell
10
comprises a doped polysilicon layer
15
and a conducting layer
17
made of a WSi
x
silicide wherein the doped polysilicon layer
15
is further used as a bit line plug
23
for electrically connecting the source
22
of the transistor
14
.
However, in the manufacturing process or during practical operation for the DRAM cell
10
, the dopants will undergo thermal diffusion both in the doped polysilicon layer
15
and source region
22
. The thermal diffusion will induce the doping region of the source
22
to expand and then diminish the L
eff
(effective channel length) between the source region
22
and drain region
24
as well as give rise to hot electron effects that will induce electrical breakdown. These conditions will reduce the threshold voltage between the source region
22
and drain region
24
, and generate small leakage currents and errors.
Hence the present invention provides a method for controlling the dopant density of the plug-shaped doped polysilicon layer and preventing dopant diffusion to other contact regions to solve those mentioned above problems.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method for controlling the dopant density of the plug-shaped doped polysilicon layer and preventing the dopants diffusing to other contact regions to solve those mentioned above problems.
In a preferred embodiment, a plug-shaped doped polysilicon layer within a plug-shaped recess is formed within a dielectric layer which is positioned above the conductive layer wherein the method for controlling the dopant contained within the plug-shaped doped polysilicon layer from diffusing into a conductive layer under the plug-shaped recess through a bottom side of the plug-shaped recess comprises the following steps:
(1). forming an undoped silicon layer on the surface of the plug-shaped recess;
(2). forming a doped polysilicon layer on top of the undoped silicon layer to fill the plug-shaped recess; and
(3). performing a thermal treatment on the semiconductor wafer so as to make the doped poly-silicon layer interact with the undoped silicon layer inside the plug-shaped recess to form a completely doped polysilicon layer within the plug-shaped recess.
It is an advantage of the present invention that the dopant density of the plug-shaped doped polysilicon layer is carefully controlled which prevents the dopants from diffusing to other contact regions.
This and other objectives and the advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5668051 (1997-09-01), Chen et al.
patent: 5759905 (1998-06-01), Pan et al.
patent: 5940733 (1999-08-01), Beinglass et al.
patent: 5976961 (1999-11-01), Jung et al.
Fan Der-Tgyr
Jou Chou-Shin
Tsai Chung-Shih
Wang Tings
Chaudhari Chandra
Kilday Lisa
Mosel Inc.
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