Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-31
2002-05-07
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S255000, C438S618000
Reexamination Certificate
active
06383868
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to methods of forming contact structures and container structures and more specifically to a process of forming a container using a simplified contact formation method which advantageously simultaneously provides local interconnect contacts.
BACKGROUND OF THE INVENTION
As semiconductor devices get smaller in size, designers are faced with problems associated with the production of capacitors which consume a small enough amount of surface area to meet design criteria, yet maintain sufficient capacitance in spite of this smaller size.
One type of capacitor that has proven successful in this regard is the container capacitor which is so named for its container-like appearance. Heretofore designers of semiconductor devices, and in particular container capacitors, have focused their attention on increasing the surface area of the inner capacitor plate to increase capacitance. Depositing polysilicon which has a rough surface texture on the inside of the containers, for example, hemispherical grain polysilicon (HSG), increases the surface area of the inner capacitor plate, and translates into the desired increased capacitance.
While the use of the technique, such as described above, initially proved successful, more recently as the lateral dimension of containers has become smaller in size, the use of materials such as HSG polysilicon becomes less attractive because the rough outer surface of such materials facilitates plugging or otherwise occluding the smaller contact openings of such containers. Accordingly, it becomes necessary to reduce the grain size or roughness of the HSG which, in turn, reduces the area enhancement factor of the film.
One type of integrated circuitry which utilizes capacitors is memory, such as dynamic random access memory (DRAM) circuitry. As DRAMs increase in memory cell density, it becomes an increasingly difficult challenge to maintain sufficiently high storage capacitance despite the decreasing cell lateral dimension necessary to achieve the higher cell density. Additionally, there is a continuing goal to further decrease cell area. One possible method of increasing cell storage capacitance is by increasing the height of the container. In this manner, a higher storage capacitance is possible without increasing the surface area such a container consumes. However, increasing the height of the container also increases the height/aspect ratio of the various contacts that must be made. Previously known methods for forming such high height/aspect ratio contacts are generally unsatisfactory, making their use problematic.
Therefore it would be advantageous to provide integrated circuitry device capacitors in containers having sufficiently high storage capacitance for advanced devices, despite decreasing device dimensions. It would also be advantageous to provide memory circuitry, and in particular DRAM circuitry, with capacitors in containers having sufficiently high storage capacitance despite decreasing cell area. In addition it would be advantageous if the methods for forming such container capacitors facilitated formation of contacts and provided for enhanced local interconnect contact formation.
SUMMARY
Methods for forming contact structures and container structures, as well as integrated circuits that can be formed by employing those methods are provided. Some embodiments of such methods, in accordance with the present invention, encompass providing a semiconductor substrate with a first insulative layer formed over the substrate and a second insulative layer formed over the first insulative layer. Formed within the first insulative layer are a plurality of first contact structures having a first conductivity type.
In some embodiments of the present invention, after forming the second insulative layer, second contact structures are formed within both the second insulative layer and the first insulative layer. In addition, at least one container structure, overlying at least one of the plurality of first contact structures, is formed within the second insulative layer. Some embodiments of the present invention form the second contact structures and the at least one container structure separately, such separate formation including separately forming conductive material that is disposed within each structure. The separate forming of conductive material provides for forming capacitor structures within the containers structures and a distinctive contact plug material within the contact structures. In some embodiments at least one of the second contact structures electrically contacts a conductive region within a P-peripheral region of the substrate and the capacitor structure electrically contacts at least one of the first contact structures. The first contact structures having been previously formed in electrical contact with conductive regions within a memory array region of the substrate.
In some embodiments a plurality of third contact holes and at least one fourth contact hole are formed and subsequently concurrently filled with a conductive material. In some embodiments, such fourth hole extends into the first insulative layer to expose a portion of a gate structure within an N-peripheral region. In some embodiments in accordance with the present invention, the filling of the third and fourth contact holes with a conductive plate material forms a layer of such conductive material overlying the second insulative layer, this layer of conductive material then being transformable into local interconnect structures.
Embodiments in accordance with the present invention generally include a third insulative layer formed overlying the second insulative layer and, where formed, the local interconnect structures. The third layer of insulative material encompasses a plurality of fifth and sixth contact holes formed therein. Such fifth and sixth contact holes for making electrical contact to the third and fourth contact structures as well as to the local interconnect structures. The fifth and sixth contact holes are generally filled with a conductive material such as a tungsten material or a combination of a barrier material such as titanium nitride and a tungsten material.
Embodiments of the present invention include any and all of the structures described herein below, as well as integrated circuit devices that are within the scope and spirit of the teachings herein, such devices formed by employing the methods and structures of embodiments of the present invention as well as modifications of such methods and structures made possible by the teachings herein.
REFERENCES:
patent: 6025226 (2000-02-01), Gambino et al.
patent: 6258649 (2001-07-01), Nakamura et al.
Parekh Kunal R.
Zahurak John K.
Tsai Jey
Wells St. John P.S.
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