Method of fabricating a semiconductor device

Details Method of fabricating a semiconductor device Method of fabricating a semiconductor device

1999-04-27

2002-05-14

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S586000, C438S587000, C438S672000, C438S691000

Reexamination Certificate

active

06387759

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating semiconductor device, and in particular, to a method of forming contacts or plugs in semiconductor device.
2. Background of the Related Art
Width of a wire and an unit cell area on a chip decrease as semiconductor device integration increases. Alignment tolerance between a gate and a contact hole, for example, that exposes an impurity region for a source/drain junction of a cell is important because it has a direct influence on an yield and allows little alignment error.
Self-Aligned Contact (SAC) is a related art technique to prevent misalignment between a gate and a contact hole due to the reduced cell area. SAC can form a contact hole exposing an impurity region without exposing a gate, despite misalignment. SAC forms a sidewall spacer and a capping insulating layer on the side and upper surfaces of the gate using an insulating substance having an etch selectivity different from an insulating interlayer. In SAC, the gate is not exposed in spite of misalignment because the etch selectivity between the insulating interlayer and the capping insulating layer or the sidewall spacer is high.
FIG. 1
is a diagram that shows a layout of a related, art semiconductor device. Referring to
FIG. 1
, a field insulating layer
102
is formed on a semiconductor substrate
100
to define an active area of a device. A plurality of word lines (gate lines) overlap the active area and the field insulating layer
102
and are formed in a direction perpendicular to the active area on the semiconductor substrate
100
. In this case, a first cap insulating layer
108
and a sidewall spacer
112
are formed on an upper surface and at the side of the gate
106
, respectively.
An impurity region
110
doped with impurity ions having a type opposite to the substrate
100
is formed in the active area around both sides of the gate
106
to be a source/drain region. A first insulating interlayer
114
having an etch selectivity different from that of the first cap insulating layer
108
and the sidewall spacer
112
is formed to cover the above structure on the semiconductor substrate
100
. First contact holes
115
and
116
exposing the impurity region
110
are formed in the first insulating interlayer
114
. The first contact holes
115
and
116
are formed in a self-aligned manner because of the etch selectivity between the first insulating interlayer
114
and the first cap insulating layer
108
or the sidewall spacer
112
. The first contact hole
115
exposes a portion of the field insulating layer
102
as well as the impurity region
110
. However, the other first contact hole
116
exposes only the impurity region
110
. First plugs
118
and
119
are formed in the first contact holes
115
and
116
to contact the impurity region
110
.
FIG. 2A
to
FIG. 2C
are diagrams that show cross-sectional views of fabricating a related art semiconductor device in accordance with a cutting line I—I in FIG.
1
.
FIG. 3
is a diagram that shows a three-dimensional view of a related art SAC process step. Referring to
FIG. 2A
, an active area is defined by forming a field insulating layer
102
in a P-typed semiconductor substrate
100
with a shallow trench isolation method (STI).
A gate oxide
104
is formed by thermally oxidizing an exposed portion of the semiconductor substrate
100
. Silicon nitride and impurity-doped polycrystalline silicon are formed on the field insulating layer
102
and the gate oxide layer
104
by chemical vapor deposition (CVD).
The silicon nitride and polycrystalline silicon are patterned by photolithography. The polycrystalline silicon becomes a gate
106
and the silicon nitride becomes a first cap insulating layer
108
. An impurity region
110
for a source/drain region is formed by implanting N-type impurities in the exposed portion of the active area on the semiconductor substrate
100
using the first cap insulating layer
108
as a mask.
Referring to
FIG. 2B
, a sidewall spacer
112
is formed at the sides of the gate
106
and the first cap insulating layer
108
. The sidewall spacer
112
is formed by depositing an insulating substance having the same etch rate as the first cap insulating layer
108
. Accordingly, silicon nitride or the like is deposited on a whole surface of the above structure and then, the insulating substance is etched with reactive ion etch (RIE) or the like to expose the impurity region
110
.
A first insulating interlayer
114
is formed by either depositing silicon oxide such as Undoped Silicate Glass (USG), Phosphor Silicate Glass (PSG), Borophospho Silicate Glass (BPSG), Tetra Ethyl Ortho Silicate (FEOS) or the like or coating the semiconductor substrate
100
with Spin On Glass (SOG) to cover the first cap insulating layer
108
and the sidewall spacer
112
. First contact holes
115
and
116
, which expose the impurity region
110
, are formed by patterning the first insulating layer
114
with photolithography. In this case, the contact holes may be formed by SAC as an etch rate of the first cap insulating layer
108
or the sidewall spacer
112
is different from that of the first insulating interlayer
114
.
The first contact holes
115
and
116
are formed by coating the first insulating interlayer
114
with a photoresist
117
, by patterning the photoresist
117
as shown in Pig.
3
, and etching the first insulating interlayer
114
using the photoresist
117
as a mask. The first contact hole
115
is formed to expose both portions of the field insulating layer
102
and the impurity region
110
, while the other first contact hole
116
is formed to expose only the impurity region
110
.
Referring to
FIG. 2C
, polycrystalline silicon doped with impurities is deposited on the first insulating interlayer
114
by CVD to fill up the first contact holes
115
and
116
. First plugs
118
and
119
are formed by etching back the polycrystalline silicon with a chemical-mechanical polishing (CMP) method to expose the first insulating interlayer
114
. Thus, the first plugs
118
and
119
are only within the contact holes
115
and
116
.
The first plug
118
contacts the impurity region
110
in the first contact hole
115
and also extends to the field insulating layer
102
, while the other first plug
119
contacts the impurity region in the second contact hole
116
. The extended part of the first plug
118
, not shown in the drawing, contacts a bitline perpendicular to the gate
106
over the field region.
FIG. 4A
to
FIG. 4D
are diagrams that show cross-sectional views of a related art method of fabricating a semiconductor device that carries out a process in a cell region CA
1
and a peripheral region PA
1
simultaneously. Reference numbers of identical elements in
FIG. 2A
to
FIG. 2C
are the same.
Referring to
FIG. 4A
, an active area of a device is defined by forming a field insulating layer
102
with an STI method in a P-type semiconductor substrate
100
having a cell region CA
1
and a peripheral region PA
1
. A gate oxide
104
is formed by thermally oxidizing an exposed portion of the semiconductor substrate
100
. Silicon nitride and polycrystalline silicon, which is doped with impurities, are formed on the field insulating layer
102
and the gate oxide layer
104
by CVD. The silicon nitride and polycrystalline silicon are patterned by photolithography. The polycrystalline silicon becomes gates
106
and
120
and the silicon nitride becomes a first cap insulating layer
108
. An impurity region
110
for a source/drain region of a memory cell and a lightly-doped impurity region
122
for an lightly doped drain (LDD) of a driving cell are formed in the cell region CA
1
and the peripheral region PA
1
, respectively, by implanting N-typed impurities lightly in the exposed portions of the active area on the semiconductor substrate
100
using the first cap insulating layer
108
as a mask. Referring to
FIG. 4B
, a sidewall spacer
112
is formed at the sides of the gate
106
and the first c

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