Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-09
2002-03-05
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S404000, C438S424000
Reexamination Certificate
active
06352897
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device. More particularly, the invention relates to a method for improving the edge recess problem of a shallow trench isolation (STI) structure.
2. Description of the Related Art
An integrated circuit (IC) is composed of many devices and isolation structures that isolate the devices. The isolation structures, such as STI structure or field oxide isolation structure, are used to prevent carriers from moving between devices. Conventionally, the isolation structures are formed within a concentrated semiconductor circuit, for example, between adjacent field effect transistors (FET) in a dynamic random access memory (DRAM), to reduce a current leakage produced by the FET.
In the booming development of the IC, it has become necessary to minimize and integrate the device. As the size of the device is scaled down with an increased integration, the isolation structure between the devices also needs to be scaled down. Of the many different methods to isolate the devices, a scalable STI is a better isolation technology for the deep sub-micron complementary metal oxide semiconductor (CMOS) process.
STI is an isolation method that forms a trench in the substrate by anisotropic etching and subsequently filling the trench with a SiO
x
layer in order to complete the isolation of the devices.
FIG.
1
A and
FIG. 1B
are schematic cross-sectional views showing the process flow of STI fabrication in the prior art.
Referring to
FIG. 1A
, a patterned pad oxide layer
102
and SiN
x
layer
104
are formed on a substrate
100
. With the pad oxide layer
102
and the SiN
x
layer
104
serving as the mask, etching is performed to form a trench
106
in the substrate
100
, so that a part of the substrate
100
is exposed. A liner oxide layer is formed by thermal oxidation on the substrate surface in the trench
106
, followed by forming a SiO
x
layer
110
that fills the trench
106
and covers the exposed substrate
100
as well as the SiN
x
layer
104
.
Referring to
FIG. 1B
, chemical mechanical polishing (CMP) is performed with the SiN
x
layer
104
acting as an etching stop to remove the excess SiO
x
layer
110
, so that the SiO
x
layer
110
remains in the trench
106
only. The SiN
x
layer
104
is removed by etching while the pad oxide layer
102
is removed by a HF solution, leaving the SiO
x
layer
110
a
in the trench
106
to form a STI structure.
In the STI process described above, the SiO
x
layer
110
a
and the liner oxide layer
108
are formed in the trench
106
. During the wet etching process which etch the pad oxide layer
102
with a HF solution, a recess
116
is formed on a top corner
114
of the STI
112
due to isotropic over-etching with the HF solution. Subsequently, the thickness of the gate oxide layer formed at the top corner
114
is thinner than the gate oxide layer formed on the active region (not shown), leading to a kink effect which causes a MOS transistor to produce a sub-threshold leakage. Furthermore, the depth of the recess
116
can be deepened with frequent use of the HF solution during the removal process of the multiple SiO
x
layer, such as removal of the sacrificial oxide layer, the tunnel oxide in the flash memory, and the dielectric layer (ONO layer) in the capacitor.
When the self-aligned silicide (salicide) process is performed on the STI with the recess structure, not only is the metal silicide layer formed in the adjacent source/drain region (not shown), but it also extends to a part of sidewall
118
of the substrate
100
(shown in
FIG. 1A
) exposed by the edge recess
116
of the STI. This causes the sidewall
118
of the substrate
100
to become a conducting layer, thus a serious junction leakage of the current occurs if the depth of the recess
116
exceeds the junction depth of the source/drain region.
As the STI with the recess is applied in a borderless contact, a Ti layer (glue layer) at the bottom of the borderless contact is adjacent to the exposed sidewall of the substrate
118
because the borderless contact is formed at the edge between the source/drain region and the STI. This leads to junction leakage of the current.
SUMMARY OF THE INVENTION
The invention provides a method to improve the edge recess of the STI. A substrate comprises of a STI with a recessed top corner, which exposes a part of a sidewall of the substrate. An insulating layer having a gap-filling capability is formed to cover the substrate and to fill the edge recess at the top corner. A part of the insulating layer over the substrate is removed, leaving a remaining part of the insulating layer to fill the edge recess and to cover the exposed sidewall of the substrate. The self-aligned metal silicide (salicide) process or borderless contact process is then performed.
As the exposed sidewall surface of the substrate is covered by the insulating layer in the edge recess, the junction leakage problem caused by applying the subsequent metallization to expose the sidewall of the substrate in the edge recess is improved.
REFERENCES:
patent: 5118641 (1992-06-01), Roberts
patent: 5393694 (1995-02-01), Mathews
patent: 5672538 (1997-09-01), Liaw et al.
patent: 5686346 (1997-11-01), Duane
patent: 5956598 (1999-09-01), Huang et al.
patent: 6110796 (2000-08-01), Sung
patent: 6140216 (2000-10-01), Richart et al.
patent: 6245637 (2001-06-01), Tsai
J. C. Patents
Jones Josetta I.
Niebling John F.
United Microelectronics Corp.
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