Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-09-29
2002-07-23
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C365S221000, C365S230060, C365S230080, C365S236000, C365S239000
Reexamination Certificate
active
06425103
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of digital electronic memory devices, and in particular to a built-in self test module for testing these devices in the field. More particularly, the invention relates to a programmable address generator suitable for implementing moving inversion algorithms.
2. Description of the Related Art
It is common practice for the manufacturers of memory chips to test the functionality of the memories at the manufacturing site. After the chips have been tested and certified for shipment, upon sale to the users, the users generally depend upon the reliability of the chips for their own systems to function properly. As the line width of memory cells within a memory array circuit chip continue to shrink (now at less than half a micron), this reliability becomes more difficult to achieve. One of the challenges for the manufacturers of memory devices, is to increase memory capacity without decreasing chip yields due to malfunctioning parts.
Before the memory chips are released for shipment, they typically undergo testing to verify that each of the memory cells within the memory array is functioning properly. This testing method is routinely done because it is not uncommon for a significant percentage of the memory cells within the chip to fail, either because of manufacturing defects or degradation faults.
In the past, chip memories have been tested using an external memory tester or Automatic Test Equipment (ATE) at the manufacturing site. This testing technique is not available to users once the chips have been shipped, making it difficult to detect faulty memory cells at the user site. Even if test equipment is available to users, field repairs are expensive, time-consuming, and impractical.
In conjunction with testing at the manufacturing site, some repairs of memories have also been performed at the manufacturing site. Conventional repairing techniques bypass the defective cells using fuseable links that cause address redirection. However, these techniques require significant capital investment for implementing the technical complexity of the repairing process, and moreover, fail to address the possibility of failure after shipment from the manufacturing facility.
Because of the difficulty of field repairs, some memory chips have been equipped with built-in self test (BIST) and built-in self repair (BISR) circuitry. As used herein, the term “BIST” refers to the actual test, while “BIST module” and “BIST circuitry” refer to the circuitry that performs BIST. Similarly, “BISR” refers to the process of built-in self repair, while “BISR module” and “BISR circuitry” refer to the circuitry that performs BISR. BIST operates by writing and reading various patterns to/from the memory to determine various kinds of memory faults. In general, a BIST module writes a data value to a memory cell and subsequently reads the memory cell. By comparing the data written and the data subsequently returned from the memory cell, the BIST module is able to determine whether the memory cell is faulty. If failing cells are present, the BISR circuitry reassigns the row or column containing the failing cell to a spare row or column in the memory array. Generally, BIST and BISR are performed each time power is applied to the system, and thus, latent failures that occur between subsequent system power-ups may be detected in the field.
Several classes of fault detection methods are well known, as illustrated by E. R. Hnatek in “4-Kilobit Memories Present a Challenge to Testing”,
Computer Design
, May 1975, pp. 117-125, which is hereby incorporated herein by reference. As Hnatek discusses, there are several considerations that should be taken into account when selecting a fault detection method, including fault coverage and length of the test procedure. Also, since no practical method provides complete coverage, the suitability of the various methods for detecting particular types of faults should be considered.
One class of methods which may provide significantly better coverage with only a small increase in the number of steps over the popular Marching 0's and 1's class is the Moving Inversions class. As described in J. H. de Jonge and A. J. Smulders in “Moving Inversions Test Pattern Is Thorough, Yet Speedy”, which is hereby incorporated herein by reference, the Moving Inversions method is as follows. The memory has 2
n
words (n is the number of address bits) that are initially loaded with 0's. The address is sequenced through all the addresses, and at each address, the memory word is first read to verify the presence of all zeros, then written with all ones, and then read to verify the presence of all ones. After the memory is filled with ones, this process is then repeated with ones and zeros exchanged. These two processes are repeated or a total of 2n different addressing sequences. The 2n sequences are generated by changing he address increment (n increments) and direction (2 directions), so that the increments for the sequences are +2
i
, 0<i<n. Every overflow generates an end-around carry, so that all addresses are tested once in each sequence. This results in 12·B·n·2
n
tests, where B is the number of bits in each word. Some variations of this method include using different data patterns (e.g. checkerboard, alternating columns, alternating rows) and adding checks and rewrites of previous and/or subsequent addresses. Other variations may include using only a selected few of the address sequences. Generally, the class of Moving Inversion methods may be characterized by the use of two or more address sequences with increments of the form ±2
i
, 0<i<n, and end-around carry.
A potential problem with using a Moving Inversion method for BIST lies in the hardware requirements for generating the address sequences. The popularity of the Marching 0's/1's is at least in part due to the simplicity of the addressing sequence which can be generated with a counter. The Moving Inversion method apparently requires an n-bit adder to add a selectable increment to each address. This is undesirable, as it is necessary to maximize the BIST speed, and fast adders require an excessive increase in hardware complexity. Unless a better solution can be found, the advantages of the Moving Inversion methods will be foregone in favor of the faster, but less effective, Marching 0's/1's methods. End users will be forced to expend more money and effort to eliminate unreliable components.
SUMMARY OF THE INVENTION
Accordingly, there is disclosed herein a low-complexity method and apparatus for generating address sequences for the moving inversion test method. In one embodiment, the address sequence generator includes a ring of counter cells in which each cell is configured to provide a toggle signal to a subsequent cell. Each cell receives a distinct least significant bit selector signal which, when asserted, designates the subsequent cell as the least significant bit. When the least significant selector signal is asserted, the cell continuously asserts the toggle signal to the subsequent cell. When the selector signal is de-asserted, the cell asserts the toggle signal to the subsequent cell half as often as the toggle signal from the preceding cell. Each cell provides an output address bit which is toggled whenever the toggle signal from the preceding bit is asserted across a transition in a clock signal. This configuration causes the ring of cells to implement a counter with a selectable least significant bit. As discussed herein, each cell may be implemented using only a toggle flip-flop and two logic gates. The addition of a direction signal and a third logic gate per cell makes the address sequencer bi-directional.
REFERENCES:
patent: 5452261 (1995-09-01), Chung et al.
patent: 5822228 (1998-10-01), Irrinki et al.
patent: 5883905 (1999-03-01), Eastburn
patent: 5909404 (1999-06-01), Schwarz
patent: 5978944 (1999-11-01), Parvathala et al.
4-Kilobit Memories Present a Challenge to Testing, Eug
Conley Rose & Tayon
LSI Logic Corporation
Moise Emmanuel L.
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