Method of forming integrated circuitry

Details Method of forming integrated circuitry Method of forming integrated circuitry

1999-03-01

2002-04-02

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S648000, C438S685000

Reexamination Certificate

active

06365507

ABSTRACT:

TECHNICAL FIELD
This invention relates to methods of depositing nitrogen enriched metal layers, to methods of forming silicide contacts to silicon comprising substrates, to methods of forming metal source layers in integrated circuits, to methods of analyzing impact of operating parameter changes for plasma deposition reactors having an inductive coil positioned therein, and to methods of forming integrated circuitry.
BACKGROUND OF THE INVENTION
In the processing of integrated circuits, electrical contact is typically made to isolated active device regions formed within a wafer substrate typically comprising monocrystalline silicon. The active regions are typically connected by electrically conductive paths or lines which are fabricated above an insulative material formed over the substrate surface. Further, electrical contact is also typically made to other conductive regions received outwardly of the wafer, such as to conductive lines, contact plugs and other devices. To provide electrical connection between two conductive regions, an opening in an insulative layer is typically etched to the desired regions to enable subsequently formed conductive films to make electrical connection with such regions.
The drive for integrated circuits of greater complexity, performance and reduced size has driven designers to shrink the size of devices in the horizontal plane. Yet to avoid excessive current density, the horizontal scaling has not necessarily been accompanied by a reduction in the vertical dimension. This has resulted in an increase of the ratio of device height to device width, something generally referred to as aspect ratio, and particularly with respect to contact openings. Such currently ranges from 1.0 to 5, and is expected to increase. The circuit density increase places increasing constraints on the conductivity of the contacts themselves.
As transistor active area and other device dimensions approached 1 micron, conventional process parameters resulted in intolerable increased resistance between the active region or device area and the conductive layer. A principal way of reducing such contact resistance is by formation of a metal silicide atop the active area prior to application of the conductive film for formation of the conductive runner. Common metal silicides are refractory metal silicides, such as TiSi
x
, where “x” is predominately 2. The TiSi
x
material is typically provided by first applying a thin layer of titanium atop the wafer which contacts the silicon containing active areas within the contact openings. Thereafter, the wafer is subjected to a high temperature anneal. This causes the titanium to react with the silicon of the active area, thus forming the TiSi
x
. Such a process is said to be self-aligning, as the TiSi
x
is only formed where the titanium metal contacts silicon. The applied titanium film typically everywhere else overlies an insulative, and substantially non-reactive, SiO
2
layer. After the first annealing, unreacted titanium may be removed selectively relative to the formed silicide by a wet etch. Further, a post-silicidation anneal might be conducted to lower sheet resistance of the formed silicide.
In the silicidation process, silicon from contact regions of the substrate diffuses upward into the refractory metal layer. Similarly, the refractory metal diffuses into the underlying silicon. The intent is for the titanium and silicon to react with each other to form a silicide thick enough to provide low sheet resistance and make a highly conductive contact interface. As a result, the doped active area of the silicon substrate (or other silicon construction) becomes thinner due to the consumption of silicon during the reaction. The resultant silicide is said to intrude or sink into the substrate or device. Over-consumption of the underlying silicon can be problematic for any silicon circuit element, tending to cause voids and thus device failures. Tendency in the industry is to make shallower and shallower active area junctions in the silicon substrates. In some instances, silicide contacts of sufficient thickness cannot be formed without completely destroying a junction because of silicon consumption from the underlying substrate.
The invention was principally motivated in addressing these problems, but is not so limited and has other applicabilities as will be appreciated by the artisan.
SUMMARY
In certain aspects, the invention encompasses one or more of a) methods of depositing nitrogen enriched metal layers, b) methods of forming silicide contacts to silicon comprising substrates, c) methods of forming metal source layers in integrated circuits, d) methods of analyzing impact of operating parameter changes for plasma deposition reactors having an inductive coil positioned therein, and e) methods of forming integrated circuitry.
In one implementation, a method of depositing a nitrogen enriched metal layer over a semiconductor substrate includes providing a sputter deposition reactor chamber having an inductive coil positioned therein, a metallic target position therein, and a semiconductor substrate positioned therein. A nitrogen containing source gas and a sputtering gas are fed to the reactor chamber. The reactor is operated to provide a selected target power, inductive coil power and substrate bias during the feeding effective to deposit an MN
x
comprising layer on the substrate, where “M” is an elemental metal and “x” is greater than 0 and less than 1. One implementation also includes forming a silicide contact to silicon from such layer, preferably with a silicon layer being formed over the MN
x
comprising layer.
In one implementation, a method of forming a metal source layer in an integrated circuit, where the metal source layer includes a metal and a non-metal impurity, includes selecting a sputtering ambient for a sputter deposition reactor having an inductive coil positioned therein to achieve within about 15% of a maximal resistivity for unsaturated metal layers having the same metal and non-metal impurity. A metallic target is then sputtered in the selected ambient within the reactor.
Preferred implementations of the above and other aspects of the invention are described below.


REFERENCES:
patent: 4746219 (1988-05-01), Holloway et al.
patent: 4863559 (1989-09-01), Douglas
patent: 4994402 (1991-02-01), Chiu
patent: 5032233 (1991-07-01), Yu et al.
patent: 5043300 (1991-08-01), Nulman
patent: 5084406 (1992-01-01), Rhodes et al.
patent: 5094977 (1992-03-01), Yu et al.
patent: 5147819 (1992-09-01), Yu et al.
patent: 5187122 (1993-02-01), Bonis
patent: 5196360 (1993-03-01), Doan et al.
patent: 5236865 (1993-08-01), Sandhu et al.
patent: 5278098 (1994-01-01), Wei et al.
patent: 5296404 (1994-03-01), Akabori et al.
patent: 5326404 (1994-07-01), Sato
patent: 5341016 (1994-08-01), Prall et al.
patent: 5378641 (1995-01-01), Cheffings
patent: 5391520 (1995-02-01), Chen et al.
patent: 5480814 (1996-01-01), Wuu et al.
patent: 5481129 (1996-01-01), DeJong et al.
patent: 5589417 (1996-12-01), Jeng
patent: 5593511 (1997-01-01), Foster et al.
patent: 5627102 (1997-05-01), Shinriki et al.
patent: 5654235 (1997-08-01), Matsumoto et al.
patent: 5683930 (1997-11-01), Batra et al.
patent: 5756394 (1998-05-01), Manning
patent: 5766997 (1998-06-01), Takeuchi
patent: 5776831 (1998-07-01), Padmanabhan et al.
patent: 5783478 (1998-07-01), Chau et al.
patent: 5925225 (1999-07-01), Ngan et al.
patent: 5985759 (1999-11-01), Kim et al.
patent: 6074921 (2000-06-01), Lin
patent: 6080665 (2000-06-01), Chen et al.
patent: 6117761 (2000-09-01), Manning
patent: 6156647 (2000-12-01), Hogan
patent: 0 631 309 (1994-12-01), None
patent: 0 631 309 (1994-12-01), None
patent: 06-010673 (1994-01-01), None
Byun, Jeong Soo et al., “Formation Of A Large Grain Sized TiN Layer Using TiNx, The Epitaxial Continuity At The A1/TiN Interface . . .”,J. Appl. Phys., 78(3), pp. 1719-1724 (Aug. 1995).
Byun, Jeong Soo, “Epitaxial C49-TiSi2Formation On (100)Si Substrate Using TiNx, And Its Electrical Characteristics As A Shallow Contact Metallization”,J. Electrochem. Soc., vol

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