Folded-bitline dual-port DRAM architecture system

Details Folded-bitline dual-port DRAM architecture system Folded-bitline dual-port DRAM architecture system

2000-09-19

2002-09-03

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S063000

Reexamination Certificate

active

06445638

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of integrated circuit (IC) design. Specifically, it relates to a folded-bitline dual-port dynamic random access memory (DRAM) architecture system.
BACKGROUND OF THE INVENTION
Each memory cell in a dual-port static random access memory (SRAM) chip is a buffer or flip-flop, and data is retained as long as power is maintained to the chip. SRAMs are realized with a bipolar technology, such as TTL, ECL, or I
2
L or with MOS technology, such as NMOS or CMOS. Bipolar SRAMs are relatively fast, having access times of 10 to 100 nsec. Power dissipation is also high, typically, 0.1 to 1.0 mW/bit. By contrast, MOS RAM access time is typically 100 nsec and power dissipation is 25 &mgr;W/bit. The combination of high circuit density, low power dissipation, and reasonable access time has led to the dominance of MOS technology in the manufacture of RAM. Hence, dual-port SRAMs having high-speed buffers are widely used in devices and equipment necessitating high-speed and high performance, such as microprocessors, communication networks, facsimile machines, modems, etc.
Since the memory cells of SRAMs take up a relatively large surface area on a single integrated (IC) chip, IC design engineers, in an effort to increase the number of memory cells on the IC chip and make the chip smaller, have focused on improving dynamic RAM (DRAM) chips to make them suitable for high-speed, high performance devices and equipment. Currently, the ultimate in compactness, is a single-port DRAM chip where each memory cell uses a capacitor to store a charge and one transistor to gate it to sense amplifier circuits as shown by the prior art DRAM cell
10
of FIG.
1
.
The DRAM cell
10
includes an access transistor
12
, a storage capacitor
14
, a bitline
16
and a wordline
18
. During a write access, a wordline enable signal is asserted on wordline
18
thereby turning on transistor
12
. A data signal is provided on bitline
16
. This signal is routed through transistor
12
and stored in capacitor
14
. During a read access, a wordline enable signal is asserted on wordline
18
to turn on transistor
12
. The data signal stored in capacitor
14
is routed to bitline
16
through transistor
12
. This data signal is amplified by a sense amplifier circuit (not shown) and then provided to the device initiating the read access.
A disadvantage of the single-port DRAM cell
10
is that it does not enable multi-port access, where more than one port can be accessed for simultaneously enabling reading, writing and/or refreshing of the memory cell. Multi-port access is required if the DRAM chip is to compete with or surpass the SRAM chip in terms of high-speed and high performance, while being simple and compact. Further, the single-port DRAM cell
10
has two additional disadvantage common to all types of DRAM cells. That is, the charge of each DRAM cell must be restored after the cell is read, and the charge in every cell must be refreshed periodically by periphery refresh circuitry.
Hence, the data rate, in terms of data access time and refresh cycle time, is low for a DRAM chip which prevents IC design engineers from implementing DRAM chips in devices and equipment requiring high-speed and high performance, such as microprocessors and communication networks. It is therefore a goal of IC design engineers to design a dual-port DRAM architecture system which can simultaneously perform two data access requests slated for a DRAM cell for increasing the data array's data rate while maintaining its compactness. Such a DRAM architecture system would be a better design choice over an SRAM architecture system for devices and equipment necessitating high-speed and high performance.
A dual-port DRAM cell is described in U.S. Pat. No. 5,923,593. The dual-port DRAM cell as shown by
FIG. 4
in the patent is designed for staggering the read accesses. That is, during the first half of a clock cycle the first port is accessed and during the second half of the clock cycle the second port is accessed. In a similar manner, write accesses can be staggered. That is, during the first half of the clock cycle, the first port is accessed for writing to a cell and during the second half of the clock cycle, the second port is accessed for writing to the same or a different cell. However, as noted in the patent, such a “simultaneous” write access results in an indeterminate data value being written to the DRAM cells which affects the integrity of the data.
For example, if in the first half of the clock cycle, a logic “one” is written into a cell while a logic “one” is latched into the sense amplifier circuit, the same row can be accessed through the second port during the second half of the clock cycle for writing a logic “zero”. At this moment, due to charge sharing between the first sense amplifier circuit and the second sense amplifier circuit, the resulting charge stored in that cell will be in between “one” and “zero” and the data in the cell has an indeterminate data value. Similarly, a read-write access could also result in the same situation. For example, if a DRAM cell is originally stored with a logic “zero”, after a read out operation through the first port during the first half of the clock cycle, a logic “zero” is latched in the first sense amplifier circuit. If the same row is accessed through the second port during the second half of the clock cycle, and is written with a logic “one”, the data in the cell will again have an indeterminate data value due to charge sharing between the first sense amplifier circuit and the second sense amplifier circuit.
Additionally, the dual-port DRAM architecture system described in U.S. Pat. No. 5,923,593 is the classical open-bitline architecture system which is known to be susceptible to noise problems due to wordline-to-bitline coupling, bitline-to-bitline coupling, and bitline-to-substrate (or well) coupling which are well known in the DRAM industry. In an effort to mitigate the noise problems, the patent discloses the use of a dummy wordline swing in the adjacent array, as well as placing a dummy load in the edge array. However, with such a design configuration, the array size is significantly increased and operation of the dual-port DRAM becomes more complex.
SUMMARY
An objective of the present invention is to provide a dual-port DRAM architecture system for overcoming the disadvantages of the prior art.
Another objective of the present invention is to provide a dual-port DRAM architecture system for simultaneously performing two access requests slated for a DRAM cell without affecting the integrity of the data.
Further, another objective of the present invention is to provide a dual-port DRAM architecture system for prioritizing two simultaneous access requests slated for a DRAM cell.
Further still, another objective of the present invention is to provide a dual-port DRAM architecture system for suppressing noise due to wordline-to-bitline coupling, bitline-to-bitline coupling, and bitline-to-substrate coupling.
Accordingly, in an embodiment of the present invention, a dual-port, folded-bitline DRAM architecture system is presented which prioritizes two simultaneous access requests slated for a DRAM cell of a data array prior to performing at least one of the access requests to prevent affecting the integrity of the data while suppressing noise due to wordline-to-bitline coupling, bitline-to-bitline coupling, and bitline-to-substrate coupling. If the two access requests are read-refresh, read-read or write-refresh, where the first access request is slated through a first port and the second access request is slated through a second port of a corresponding DRAM cell of the data array, the system prioritizes the access request slated through the first port at a higher priority than the access request slated through the second port. The system thus cancels the access request slated through the second port. If the two access requests are write-read, the system prioritizes the two access requests as being equal to each other. The s

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