Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-21
2002-09-03
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S420000, C438S528000, C438S545000
Reexamination Certificate
active
06444522
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to a method of manufacturing a flash memory device. More particularly, the present invention relates to a method of manufacturing a flash memory device capable of improving a barrier characteristic between a substrate and a well in the flash memory device.
BACKGROUND OF THE INVENTION
In general, a well region in a flash memory device is formed through the process by which ions are implanted into a semiconductor substrate and the implanted ions are then diffused by thermal process, which usually employs a triple well structure. Then, a method of manufacturing a flash memory device will be below explained by reference to
FIGS. 1A
to
1
D.
FIGS. 1A
to
1
D are cross-sectional views of a device for explaining a method of manufacturing a conventional flash memory device.
As shown in
FIG. 1A
, field oxide films
12
are formed on a semiconductor substrate
11
by device isolation process. The semiconductor substrate
11
employs a P-type substrate.
Then, as shown in
FIG. 1B
, a first photoresist pattern
13
, through which a portion of the P-type semiconductor substrate
11
in which a N-well region will be formed is exposed, is formed. Next, N-type impurity ions such as phosphorous (P) are implanted to form a N-well region
14
.
Thereafter, as shown in
FIG. 1C
, after the first photoresist pattern
13
is removed, a second photoresist pattern
15
, through which a portion of the P-type semiconductor substrate
11
in which a P-well region will be formed is exposed, is formed. Next, P-type impurity ions such as boron (B) are implanted to form a P-well region
16
.
FIG. 1D
shows a state in which a thermal process is performed, by which dopants in each of the N-well region
14
and the P-well region
16
have an electrical characteristic and regions non-crystallized by ion implantation are crystallized.
The triple well structure formed by this method is shown in FIG.
2
.
FIG. 2
is a diagram for explaining a well structure of a conventional flash memory device, which shows that a depletion region
17
is located between the N-well region
14
and the P-well region
16
.
In this triple well structure, however, as the mobility of boron (B) used as a dopant for forming the P-well region is higher than that of phosphorous (P) used as a dopant for forming the N-well region, the concentration of boron (B) must be higher upon ion implantation into the P-well region, considering reduction in the concentration due to compensation of coexisting phosphorous (P) and boron (B) when a subsequent thermal process is performed. However, as the dopant concentration in the N-well region is reduced by a count doping phenomenon of phosphorous (P) and boron (B) generated when a subsequent thermal process is performed, the concentration in the N-well region must be increased because a barrier function of the N-well region is weakened between the P-type semiconductor substrate and the P-well region. If this is done, however, as the concentration of the P-well region and the N-well region is reduced, there is a problem that the electric characteristic of the device is degraded such as reduction in the break down voltage between the wells, reduction in the insulating characteristic between the wells, etc.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of manufacturing a flash memory device which can improve a barrier characteristic between a substrate and well regions by forming an anti-diffusion region between the well regions.
In order to accomplish the above object, a method of manufacturing a flash memory device according to the present invention is characterized in that it comprises the steps of forming a semiconductor substrate in which field oxide films are formed, forming a first photoresist pattern through which a portion of the semiconductor substrate in which a first well region will be formed is exposed, on the semiconductor substrate, and then implanting an impurity ion having an opposite type to the semiconductor substrate to form a first well region, after removing the first photoresist pattern, forming a second photoresist pattern through which a portion of the semiconductor substrate in which a second well region will be formed is exposed on the semiconductor substrate, and then implanting ion implantation process to form an anti-diffusion region, implanting an impurity ion of the same type to the semiconductor substrate into the semiconductor substrate in which the second photoresist pattern is formed, thus forming a second well region, and performing a thermal process for activating impurities in the first well region, the anti-diffusion region and the second well region.
REFERENCES:
patent: 5548143 (1996-08-01), Lee
patent: 6025238 (2000-02-01), Gardner
patent: 6221724 (2001-04-01), Yu et al.
patent: 6225151 (2001-05-01), Gardner et al.
Cho Byung Hee
Kwak Noh Yeal
Chaudhari Chandra
Hyundai Electronics Industries Co,. Ltd.
Pennie & Edmonds LLP
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