Discrete devices including EAPROM transistor and NVRAM...

Details Discrete devices including EAPROM transistor and NVRAM... Discrete devices including EAPROM transistor and NVRAM...

1999-12-15

2002-01-08

Phan, Trong (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000

Reexamination Certificate

active

06337805

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to discrete elements such as electrically alterable programmable read-only memory (EAPROM) and nonvolatile random access memory (NVRAM) devices. More specifically, the present invention relates to EAPROM and NVRAM cells where data is stored using a ferroelectric capacitor incorporated in the cells. Methods for operating, writing to and reading from, such DRAM, logic devices, memory arrays, and systems containing these cells are also disclosed.
2. Description of Related Art
Dynamic random access memories (DRAMs) are the most cost-effective, high-speed memory used with present day computers. DRAMS last nearly indefinitely. Moreover, DRAMs are available in very high density configurations, e.g., 64 megabytes (MB). However, DRAMS can only store information for a limited time without constant refreshing and lose all knowledge of their state once power is removed.
Ferroelectric capacitors are currently being used as nonvolatile memory devices, as disclosed in U.S. Pat. No. 4,888,733, which is entitled “Nonvolatile Memory Cell and Sensing Method” and discloses a two transistor, one capacitor (2T/1C) memory cell. In addition, ferroelectric capacitors are often employed in nonvolatile random access memories (NVRAMs). Memory cells having structures approximating that of DRAMs, i.e., arranged in the conventional one transistor, one capacitor (1T/1C) memory cell pattern, are disclosed in U.S. Pat. Nos. 5,600,587 (Ferroelectric Random Access Memory), 5,572,459 (Voltage Reference for a Ferroelectric 1T/1C Based Memory), 5,550,770 (Semiconductor Memory Device Having FE Capacitor Memory Cells with Reading, Writing, and Forced Refreshing Functions and a Method of Operating the Same), 5,530,668 (Ferroelectric Memory Sensing Scheme Using Bit Lines Precharged to a Logic One Voltage), and 5,541,872 (Folded Bit Line Ferroelectric Memory Device). It should be mentioned that all of the patents cited above are incorporated by reference herein for all purposes.
In the above-mentioned patents, the capacitor in a 1T/1C DRAM structure is replaced by a ferroelectric capacitor, as illustrated in FIG.
1
(
a
). The memory cell
1
of FIG.
1
(
a
) includes a wordline
10
, a digitline
12
, a transistor
14
and a ferroelectric capacitor
16
. In operation, the remnant charges are detected on a bit line in a manner similar to the operation of a conventional DRAM. However, these structures are not without attendant problems.
There is an extensive body of literature on both the electrical characteristics of ferroelectric capacitors and applications in cells similar to conventional DRAMs, except that these cells are classified as nonvolatile RAMs (NVRAMs) instead of DRAMs. One recent publication by K. Asaril et al., entitled “Multi-Level Technologies for FRAM Embedded Reconfigurable Hardware” (IEEE Int. Solid-State Circuits Conf., San Francisco 1999, pp. 108-109), describes the use of a ferroelectric capacitor in a ferroelectric RAM (FRAM)which is employed with low voltage to store and access RAM data superimposed on less-frequently accessed read-only memory (ROM) data in the same cell. See U.S. Pat. No. 5,539,279, entitled “Ferroelectric Memory.” The RAM data is volatile and needs to be refreshed on a regular basis, or this aspect of the cell acts like a DRAM. The electrically alterable read-only memory (EAROM), e.g., an electrically erasable programmable ROM (EEPROM) data is nonvolatile. In other words, the FRAM acts like a DRAM with a “repressed” nonvolatile read only “memory,” or “repressed memory.”
Other applications use the ferroelectric capacitors as part of a stacked gate structure similar not to DRAMs but rather to EEPROM or flash memory devices. See, for example, U.S. Pat. Nos. 5,541,871 (“Nonvolatile Ferroelectric Semiconductor Memory”) and 5,856,688(“Integrated Circuit Memory Devices Having Nonvolatile Single Transistor Unit Cells Therein”), which patents are also incorporated herein by reference for all purposes. It will be appreciated that in these devices, however, the remnant charge or polarization charge of the ferroelectric element is used to store information rather than electrons injected onto or removed from a floating gate by hot electron effects and/or tunneling. Instead, the charge differences are not differences in the number of electrons trapped on the gate but rather the polarization charge of the upper ferroelectric capacitor.
It should also be mentioned that the prior art referenced in U.S. Pat. No. 5,541,871describes a basic structure consisting of a ferroelectric capacitor in series with a gate capacitance, which are both planar structures. As shown in FIG.
1
(
b
), a memory cell
1
′ includes a wordline
10
, a digitline
12
, a transistor
14
, and a ferroelectric capacitor
20
, one plate of the ferroelectric capacitor forming the gate of the transistor
14
.
FIG.
1
(
c
) illustrates a memory cell
1
″, which includes the wordline
10
, digitline
12
, transistor
14
, a high dielectric capacitor
30
and a ferroelectric capacitor
32
. It will be noted that the lower plate of capacitor
30
forms the control gate of the transistor
14
.
The problem with this disclosed structure is that the ferroelectric elements have very high electric permittivities as, for instance, 80 and 150 k. It will be appreciated that these permittivity values are 20 to 40 times higher than that of silicon dioxide. It will also be appreciated that, if comparable thicknesses of materials as are used in constructing the ferroelectric and conventional capacitors, only a small fraction, e.g., 2% to 5%, of the voltage applied across the series capacitors will appear across the ferroelectric capacitor. Thus, if the ferroelectric capacitor has a coercive voltage, Vc , i.e., the voltage required for programming, of 1 V or 3 V, then the total word line voltage required for programming the memory cell will be on the order 20 V to 150 V. It will be noted that these are far in excess of voltages used on current CMOS-integrated circuits.
U.S. Pat. No. 5,856,688 seeks to solve this problem by using a “C” shaped floating gate and two control gates. One control gate is a plate of the ferroelectric capacitor and the other control gate is a plate of another capacitor fabricated using a high dielectric constant material. The two capacitors in series, one with a high dielectric constant ferroelectric and the other with a high dielectric constant insulator, are used to program the ferroelectric capacitor at lower voltages. Since the capacitances are more or less comparable, the programming voltage will divide more equally, resulting in a significant fraction across the ferroelectric capacitor.
It should be mentioned that other repressed memory devices have been proposed. For example, a repressed memory where the NVRAM function is provided by a flash memory type structure for the gate of the transfer device is described in the commonly assigned, copending application entitled “DRAM AND SRAM MEMORY CELLS WITH REPRESSED MEMORY” (Ser. No. (09/362,909, filed Jul. 29, 1999), which application is incorporated herein by reference for all purposes. It will be appreciated that these memories do not function like the shadow RAM disclosed in U.S. Pat. 5,399,516 (“Method of Making a Shadow Ram Cell Having a Shallow Trench EEPROM”), storing the same information on both memory planes.
In contrast, U.S. application Ser. No.09/385,380, describes a memory cell
1
′″ having first and second operating modes. The memory cell
1
′″ includes a charge transfer transistor
14
having a gate adjacent to a channel region coupling source and drain regions, a digitline
12
coupled to one of the source and drain regions, a storage capacitor
16
coupled to the other of the source and drain regions, a ferroelectric capacitor
32
, and a wordline
10
coupled to the gate by the ferroelectric capacitor
32
. The polysilicon vertical interconnect connecting the ferroelectric capacitor
32
with oxide layer covering the gate of the tra

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