Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-12-16
2002-07-02
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S255000, C438S398000, C438S947000, C438S964000
Reexamination Certificate
active
06413831
ABSTRACT:
BACKGROUND OF THE INVENTION
1Field of the Invention
The present invention relates to a semiconductor memory device and method of fabricating same. More particularly, the present invention relates to capacitor fabrication techniques applicable to dynamic random access memories (“DRAMs”) capable of achieving an improved degree of integration and a lower number of defects within the DRAM.
2. State of the Art
A widely-utilized DRAM (Dynamic Random Access Memory) manufacturing process utilizes CMOS (Complementary Metal Oxide Semiconductor) technology to produce DRAM circuits which comprise an array of unit memory cells, each including one capacitor and one transistor, such as a field effect transistor (“FET”). In the most common circuit designs, one side of the transistor is connected to external circuit lines called the bit line and the word line, and the other side of the capacitor is connected to a reference voltage that is typically one-half the internal circuit voltage. In such memory cells, an electrical signal charge is stored in a storage node of the capacitor connected to the transistor which charges and discharges circuit lines of the capacitor.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. The advantages of increased miniaturization of components include: reduced-bulk electronic equipment, improved reliability by reducing the number of solder or plug connections, lower assembly and packaging costs, and improved circuit performance. In pursuit of increased miniaturization, DRAM chips have been continually redesigned to achieved ever-higher degrees of integration which has reduced the size of the DRAM. However, as the dimensions of the DRAM are reduced, the occupied area of each unit memory cell of the DRAM must be reduced. This reduction in occupied area necessarily results in a reduction of the dimensions of the capacitor, which, in turn, makes it difficult to ensure required storage capacitance for transmitting a desired signal without malfunction. However, the ability to densely pack the unit memory cells while maintaining required capacitance levels is a crucial requirement of semiconductor manufacturing technologies if future generations of DRAM devices are to be successfully manufactured.
In order to minimize such a decrease in storage capacitance caused by the reduced occupied area of the capacitor, the capacitor should have a relatively large surface area within the limited region defined on a semiconductor substrate. The drive to produce smaller DRAM circuits has given rise to a great deal of capacitor development. However, for reasons of available capacitance, reliability, and ease of fabrication, most capacitors are stacked capacitors in which the capacitor covers nearly the entire area of a cell and in which vertical portions of the capacitor contribute significantly to the total charge storage capacity. In such designs, the side of the capacitor connected to the transistor is generally called the “storage node” or “storage poly” since the material out of which it is formed is doped polysilicon, while the polysilicon layer defining the side of the capacitor connected to the reference voltage mentioned above is called the “cell poly.”
An article by J. H. Ahn et al., entitled “Micro Villus Patterning (MVP) Technology for 256 Mb DRAM Stack Cell,” 1992 IEEE, 1992 Symposium on VLSI Technology Digest of Technical Papers, pp. 12-13, hereby incorporated herein by reference, discusses the use of MVP (Micro Villus Patterning) technology for forming a high surface area capacitor.
FIGS. 25-28
illustrate cross-sectional views of this technique.
FIG. 25
shows a memory cell structure comprising a substrate
202
which has been oxidized to form thick field oxide areas
204
with transistor gate members
206
disposed on the surface of the substrate
202
. A barrier layer
208
is disposed over the transistor gate members
206
, substrate
202
, and field oxide areas
204
, and a silicon nitride layer
210
is disposed over the barrier layer
208
. A storage poly
212
is disposed on the silicon nitride layer
210
and extends through the silicon nitride layer
210
and the barrier layer
208
and between two transistor gate members
206
to contact the substrate
202
. A layer of silicon dioxide
214
is disposed over the storage poly
212
.
As shown in
FIG. 26
, an HSG (HemiSpherical-Grain) polysilicon layer
216
is grown on the exposed surfaces of the silicon nitride layer
210
, the storage poly
212
, and the silicon dioxide layer
214
. The structure is then etched using the HSG polysilicon layer
216
as a mask which results in very thin, closely spaced micro villus bars or pins
218
, as shown in FIG.
27
. The silicon dioxide layer
214
and the silicon nitride layer
210
are then stripped to form the structure shown in
FIG. 28. A
finalized capacitor would be formed by further processing steps including depositing a dielectric layer on the etched storage poly and depositing a cell poly on the dielectric layer.
Although the MVP technique greatly increases the surface area of the storage poly, a drawback of using the MVP technique is that it can result in splintering problems (or slivers) in the storage node cell poly. As illustrated in
FIG. 29
, the micro villus bars/pins
218
, formed in the method shown in
FIGS. 25-28
, are thin and fragile such that they are susceptible to splintering that may result in one or more of the micro villus bars/pins (such as pin
220
) falling over and shorting to an adjacent storage poly
222
, which would render the adjacent storage cells shorted and unusable.
In a 64M DRAM, for example, even if there was only one out of 100,000 cells that had a failure due to a splintered macro villus bar/pin shorting with an adjacent storage cell, it would result in 640 failures or shorts in the DRAM. Generally, there are a limited number of redundant memory cells (usually less than 640 in a 64M DRAM) within a DRAM which are available for use in place of the shorted memory cell. Thus, if the number of failures exceeds the number of redundant memory cells within the DRAM, the DRAM would have to be scrapped.
Therefore, it would be desirable to increase storage cell capacitance by using a technology such as MVP while eliminating polysilicon storage node splintering problems.
SUMMARY OF THE INVENTION
The present invention relates to a method of forming a high surface area capacitor, generally used in DRAMs. The present invention takes an opposite approach from the prior art in forming capacitors. Rather than forming bars or pins to increase the surface area, the present invention forms the opposite by etching holes or voids into the storage poly to form a honeycomb or webbed structure. Such a honeycomb/webbed structure forms a high surface area capacitor without bars or pins which could splinter and short out an adjacent storage cell, as discussed above.
Numerous methods could be employed to achieve the honeycomb structure of the present invention. One such method is a reverse MVP technique wherein an HSG polysilicon layer is grown on the surface of the storage poly and a mask layer is deposited over the HSG polysilicon layer. An upper portion of the mask layer is then removed, forming micro openings to expose the uppermost portions of the HSG polysilicon layer. The exposed HSG polysilicon layer portions are then etched, which translates the pattern of the exposed HSG polysilicon layer portions (which is generally the reverse pattern of the bars or pins which would be formed by the prior art method) into the storage poly. The capacitor is completed by depositing a dielectric material layer over the storage poly layer and depositing a cell poly layer over the dielectric material layer.
REFERENCES:
patent: 5061650 (1991-10-01), Dennison et al.
patent: 5149676 (1992-09-01), Kim et al.
patent: 5170233 (1992-12-01), Liu et al.
patent: 5254503 (1993-10-01), Kenny
patent: 5256587 (1993-10-01), Jun et al.
patent: 5278091 (1994
Clampitt Darwin A.
Green James E.
Jr. Carl Whitehead
Micro)n Technology, Inc.
Thomas Toniae M.
TraskBritt
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