Semiconductor memory device of shared sense amplifier system

Details Semiconductor memory device of shared sense amplifier system Semiconductor memory device of shared sense amplifier system

2000-08-31

2002-01-29

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S194000

Reexamination Certificate

active

06343038

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-250516, filed Sep. 3, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device. More particularly, the invention relates to the technique of screening the bit lines provided in a semiconductor memory device having a shared sense amplifier system, some of the bit lines connected to one side of a sense amplifier and conducting a leakage current and the others of the bit lines connected to the other side of the sense amplifier. The invention also relates to the technique of reducing a standby current generated from the leakage current flowing in the bit lines of such a semiconductor memory device.
In recent years, occurrence of a bit line leakage current becomes significant with an increase in the integration density of a semiconductor memory device as is represented by a leakage current occurring in a short circuit between a bit line and a word line. The short circuit between the bit line and the word line which is the main cause of the bit line leakage current causes the following problem if a dynamic RAM (DRAM) is taken as an example. That is, at the standby time, paired bit lines are kept at a preset bit line precharged potential (VBL). Generally, the precharge potential is set to half the high-level potential of the bit line. At this time, the potential of the word line is set at a low level. Therefore, if a short circuit portion occurs between the bit line and the word line, a leakage current will continuously flow from the bit line which is set at the preset precharge potential (VBL) to the word line which is set at the low level potential (for example, ground potential). As a result, the potential of the bit line which is short-circuited to the word line is lowered. The amount of a lowering in the bit line potential depends on a resistance between the short-circuited bit line and word line and the conductance of a precharge current limiting element connected to the bit line.
In this case, a special problem occurs in a case where a semiconductor memory device using a shared sense amplifier system in which the sense amplifier is commonly used for adjacent bit lines and which recently becomes dominant is used. In the semiconductor memory device using the shared sense amplifier system, a bit line disposed adjacent to and on the opposite side of a defective bit line which is short-circuited with the word line with the sense amplifier disposed therebetween is also influenced by the short circuit and the operation margin thereof is reduced, but since the amount of the reduction is small in comparison with the bit line which is short-circuited, it becomes extremely difficult to detect the bit line by effecting the screening operation. As a result, the semiconductor memory device passes a test in the wafer state, is subjected to the post process without replacing the defective bit line by a redundancy circuit and is detected defective in the product test effected after it is assembled into a package, and in the worst case, there is a possibility that it may be shipped as a product.
The product having the bit line leakage current is one of the main causes which increase the number of defective products in the market since a resistance between the bit line and the word line which are short-circuited with each other is lowered by an influence due to the deterioration with time or the like. Therefore, a method for effectively screening the bit line having the bit line leakage current is indispensable.
FIG. 1
shows the conventional semiconductor memory device and shows one example of a representative shared sense amplifier and bit line precharge/equalizing circuit. The circuit includes an N-channel sense amplifier
10
, P-channel sense amplifier
11
, bit line precharge/equalizing circuits
20
,
21
and bit switches
40
,
41
.
The bit line precharge/equalizing circuit
20
is connected to paired bit lines BLL, /BLL to precharge the paired bit lines BLL, /BLL and equalize the potentials thereof so as to set the potentials thereof to a bit line precharge potential VBL. One end of the current path of a cell transistor TN
50
is connected to the bit line BLL and the gate thereof is connected to a word line WLL. A cell capacitor C
10
is connected between the other end of the current path of the cell transistor TN
50
and the ground node. The cell transistor TN
50
and the cell capacitor C
10
are combined to form a memory cell.
The bit line precharge/equalizing circuit
21
is connected to paired bit lines BLR, /BLR to precharge the paired bit lines BLR, /BLR and equalize the potentials thereof so as to set the potentials thereof to the bit line precharge potential VBL. One end of the current path of a cell transistor TN
51
is connected to the bit line BLR and the gate thereof is connected to a word line WLR
1
. A cell capacitor C
11
is connected between the other end of the current path of the cell transistor TN
51
and the ground node. The cell transistor TN
51
and the cell capacitor C
11
are combined to form a memory cell. Further, one end of the current path of a cell transistor TN
52
is connected to the bit line /BLR and the gate thereof is connected to a word line WLR
2
. A cell capacitor C
12
is connected between the other end of the current path of the cell transistor TN
52
and the ground node. The cell transistor TN
52
and the cell capacitor C
12
are combined to form a memory cell.
The N-channel sense amplifier
10
and P-channel sense amplifier
11
are arranged adjacent to each other. The bit switch
40
is disposed between the bit line precharge/equalizing circuit
20
and the sense amplifiers
10
,
11
and the bit switch
41
is disposed between the bit line precharge/equalizing circuit
21
and the sense amplifiers
10
,
11
. Further, the current paths of column select transistors TN
30
, TN
31
are connected between the sense amplifiers
10
,
11
and paired data lines DL, /DL. A column select signal CSL is supplied to the gates of the column select transistors TN
30
, TN
31
.
The N-channel sense amplifier
10
is constructed by N-channel MOS transistors TN
11
, TN
12
and the operation thereof is controlled by an N-channel sense amplifier control signal &phgr;SN. The P-channel sense amplifier
11
is constructed by P-channel MOS transistors TP
11
, TP
12
and the operation thereof is controlled by a P-channel sense amplifier control signal &phgr;SP.
The bit line precharge/equalizing circuit
20
is constructed by N-channel MOS transistors TN
20
to TN
22
and the bit line precharge/equalizing circuit
21
is constructed by N-channel MOS transistors TN
23
to TN
25
. A precharge/equalizing circuit control signal &phgr;EQL is supplied to the gates of the MOS transistors TN
20
to TN
22
to precharge the paired bit lines BLL, /BLL and equalize the potentials thereof. A precharge/equalizing circuit control signal &phgr;EQR is supplied to the gates of the MOS transistors TN
23
to TN
25
to precharge the paired bit lines BLR, /BLR and equalize the potentials thereof.
The bit switch
40
is constructed by N-channel MOS transistors TN
40
, TN
41
and controlled by a bit switch control signal &phgr;L. The bit switch
41
is constructed by N-channel MOS transistors TN
42
, TN
43
and controlled by a bit switch control signal &phgr;R.
In
FIG. 1
, an example in which the bit line /BLR is short-circuited to the word line WLR
2
is shown and it is equivalently expressed by a resistor Rshort.
FIG. 2
is a block diagram showing an equalizing signal generation circuit
50
for generating a precharge/equalizing circuit control signal &phgr;EQL/R in the circuit shown in
FIG. 1
based on an equalizing/precharge circuit control signal &phgr;EQLCONTL/R.
FIG. 3
shows an example of the detail construction of the equalizing signal generation circuit
50
. As shown in
FIG. 3
, the equalizing signal generation circuit
50
is co

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