Semiconductor integrated circuit device with its layout...

Details Semiconductor integrated circuit device with its layout... Semiconductor integrated circuit device with its layout...

1999-09-07

2002-01-01

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Significant integrated structure, layout, or layout...

C326S041000, C257S210000

Reexamination Certificate

active

06335640

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit device having its layout designed by a cell base system, that is, by a system that lays out a logic circuit for each standard cell.
BACKGROUND ART
FIG. 1
is a layout sketch depicting a semiconductor integrated circuit device that utilizes the cell base system for its layout design. In
FIG. 1
, reference numeral
1
denotes the semiconductor integrated circuit device,
2
standard cells (hereinafter referred to also simply as cells) forming the semiconductor integrated circuit device
1
,
3
a
to
3
g
cell arrays each consisting of a predetermined number of standard cells
2
arranged side by side,
4
intercell conductors between the cells
2
and
2
,
5
I/O pads for signal input/output therethrough,
5
a
I/O conductors between the I/O pads
5
and the cells
2
,
6
power supply pads,
7
grounding pads,
8
power supply conductors, and
9
grounding conductors.
The standard cells
2
, which constitute the cell arrays
3
a
to
3
g
, include various logic circuits such as inverters, AND, OR, NAND and NOR gates and flip-flops. In
FIG. 3
there is shown an example that an inverter depicted in
FIG. 2
is the standard cell of a CMOS configuration. In
FIG. 3
, reference numeral
10
denotes a P-channel MOS transistor (hereinafter referred to as a PMOS),
11
an N-channel MOS transistor (hereinafter referred to as an NMOS),
12
a PMOS source conductor,
13
a
a PMOS gate conductor,
13
b
an NMOS-side gate conductor,
14
a common drain conductor,
15
an NMOS source conductor,
16
a cell power supply conductor,
17
a cell grounding conductor,
18
an input pin of the inverter,
19
an output pin of the inverter,
20
a
a through hole for interconnecting the input pin
18
and an Al conductor,
20
b
a through hole interconnecting the output pin
19
and the common drain conductor
14
, and
21
a through hole interconnecting the Al conductor and the gate conductors
13
a
and
13
b.
In the inverter cell depicted in
FIG. 3
, the cell power supply conductor
16
, the cell grounding conductor
17
, the PMOS source conductor
12
, the common drain conductor
14
and the NMOS source conductor
15
are a first Al wiring layer. The standard cells of NAND gates, flip-flops and so on, as well as the inverters, have their cell power supply conductors
16
and their cell grounding conductors
17
formed from the first Al wiring layer. Accordingly, adjacent cells
2
of the respective cell arrays
3
a
to
3
g
have their cell power supply conductors
16
and their cell grounding conductors
17
interconnected via the first Al wiring layer. The signal transmission between the standard cells is made via a second Al wiring layer.
In the semiconductor integrated circuit device whose layout is designed using the cell base system, the standard cell width needs to be defined since the cell arrays
3
a
to
3
g
are a side-by-side arrangement of plural standard cells
2
. It is customary in the art to set, as one basic cell width (1 BC), a width
24
which is half that
22
of the inverter cell depicted in FIG.
3
. With such a basic cell (BC), the width
22
of the inverter cell shown in
FIG. 3
is 2 BC.
On the other hand, the height
23
of the inverter cell depicted in
FIG. 3
is called the cell height, and in the cell bases system, to keep the cell arrays
3
a
to
3
g
at a fixed height is most important for continuously connecting the cell power supply conductor
16
and the cell grounding conductor
17
without a break; hence, the cell height is set at a fixed value irrespective of the kinds of standard cells used.
Next, the operation of the prior art example will be described.
A description will be given first of a method of layout design by the cell base system.
FIG. 4
is a diagram of an example in which three cell arrays
3
a
,
3
b
and
3
c
are formed by arranging side by side such standard cells as inverters, NAND gates and flip-flops. Since the cell widths of the individual standard cells are integral multiples of the basic cell width (1 BC), the widths of the cell arrays are integral multiples of 1 BC. However, the standard cells each have a different width; for example, the inverter cell width is 2 BC, the NAND cell width 3 BC and the flip-flop cell 15 BC. Therefore, the widths
26
a
,
26
b
and
26
c
of the three cell arrays
3
a
,
3
b
and
3
c
depicted in
FIG. 4
differ from one another. In the
FIG. 4
example, the width
26
b
of the cell array
3
b
and the width
26
c
of the cell array
3
c
are smaller than the longest cell array
3
a
by 4 BC and 2 BC, respectively.
To make the widths of the three cell arrays
3
a
,
3
b
and
3
c
equal, a feedthrough cell
28
shown in
FIG. 5
is used. The width
27
of the feedthrough cell
28
is 1 BC and its cell height
23
is the same as those of the other standard cells. And this cell is made up only of a power supply conductor
16
and a cell grounding conductor
17
which are formed from the first Al wiring layer.
FIG. 6
shows an example in which such feedthrough cells
28
as depicted in
FIG. 5
are inserted in the cell arrays
3
b
and
3
c
to make the widths of the three cell arrays
3
a
,
3
b
and
3
c
equal to one another. That is, four feedthrough cells
28
a
to
28
d
are additionally arranged in the cell array
3
b
and two feedthrough cells
28
e
and
28
f
are additionally arranged in the cell array
3
c
to make their array widths equal to that of the widest cell array
3
a.
The feedthrough cell
28
has a function of securing a wiring region as well as the function of providing the uniform cell array width as referred to above. This wiring region securing function will be described below. Now, consider the case where three cell arrays
3
a
,
3
b
and
3
c
of the same array width are completed by inserting appropriate numbers of feedthrough cells
28
as depicted in FIG.
6
and then a NAND cell in the cell array
3
c
and an inverter
32
in the cell array
3
a
are interconnected by a conductor
30
as depicted in FIG.
7
. In this instance, as depicted in
FIG. 8
, the conductor
30
for connecting the NAND cell
31
of the cell array
3
c
and the inverter
32
of the cell array
3
a
crosses one of four feedthrough cells
28
a
to
28
d
of the cell array
3
a
, for example, the feedthrough cell
28
b
. Since the conductor
30
is formed from a second Al wiring layer, it does not contact the cell power supply conductor and grounding conductor of the feedthrough cell
28
b
formed from the first Al wiring layer.
Next, a description will be given of a method for supplying power to and grounding each cell array. As shown in
FIG. 9
, there are placed power supply/grounding cap cells
35
at opposite ends of the cell arrays
3
a
and
3
b
. Extending across the cap cells
35
are power supply conductors
33
and grounding conductors
34
formed from the second Al wiring layer. The power supply conductors
33
and the grounding conductors
34
are connected to the power supply pads
6
and the grounding pads
7
, respectively, located on the marginal portions of the semiconductor integrated circuit device
1
.
As depicted in
FIG. 10
, a power supply conductor
33
a
formed from the second Al wiring layer on each cap cell
35
is connected via a through hole
16
a
to a cell power supply conductor
16
b
formed from the first Al wiring layer, and similarly, a grounding conductor
34
a
formed from the second Al wiring layer is connected via a through hole
17
a
to a cell grounding conductor
17
b
formed from the first Al wiring layer. Since each cap cell
35
has the construction mentioned above, power is supplied to each cell via a route [power supply conductor
33
a
-through hole
16
a
-cell power supply conductor
16
b
] and each cell is grounded via a route [grounding conductor
34
a
-through hole
17
a
-cell grounding conductor
17
b].
Since the semiconductor integrated circuit device having its layout designed by the conventional cell base system has the configuration descr

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