Method of forming thin film transistor

Details Method of forming thin film transistor Method of forming thin film transistor

2000-11-13

2002-01-22

Lebentritt, Michael (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S152000, C438S166000, C438S308000

Reexamination Certificate

active

06340609

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to the method of forming thin film transistor and more particularly related to the method of forming thin film transistor that can be used for display devices such as LCD (liquid crystal display), EL (electro luminescent display) device.
BACKGROUND OF THE INVENTION
Nowadays, the development of TFT (thin film transistor) technology is prominent. TFT is frequently used as switching device in a pixel of flat panel display like LCD and EL, and also used in module that is formed on glass substrate of the display panel.
Generally, TFT is formed on glass substrate. Semiconductor layer that is used as active layer containing channel and source/drain region of MOS (Metal Oxide Silicon) transistor is formed on glass substrate. Thus, gate pattern can be situated below the semiconductor layer as shown in bottom gate type TFTs. In bottom gate type TFTs, impurities may be doped to semiconductor layer by supplying impurity source gas when the semiconductor layer is deposited on a glass substrate.
On the other hand, in top gate type TFTs where the gate pattern is above semiconductor layer, impurity doping is executed by ion implanting. In the ion doping process, gate pattern take the role of ion implanting mask which prevent the channel region from being doped. Thus, the ions projected to channel regions are implanted in gate patterns and can be accumulated in the gate patterns which are isolated conductor patterns.
The accumulated ions raise the electrostatic potential of the gate patterns and may cause instant electric discharge accompanying spark between the gate patterns. And the spark usually destruct neighboring structure of patterns and electric isolations.
At this time, gate patterns mean a set of separated patterns including gate electrode, gate pad, gate line which are formed by patterning a gate layer. The location and separation of the gate patterns are decided by circuital arrangement of devices. And the sizes of area of the gate patterns can be varied. Above mentioned instant electric discharge usually happens between gate patterns whose sizes of area are significantly different and gap between them is small and on an active area.
FIG. 1
is planar view of part of panel substrate showing the electrostatic destruction caused by instant discharge between gate patterns. The destruction is caused when p type impurity ions generated from di-boron (mixture of B2H6 and H2) plasma are projected with the energy level of 50~65 keV and the does level of 5*10{circumflex over ( )}15/cm{circumflex over ( )}2 to transistor area of polycrystalline silicon type TFT LCD. Two long latitudinal line patterns are long gate lines and rotated cup shape pattern is a small gate pattern. Rectangular area lying across the gate patterns longitudinally is active region. In the active region, long gate patterns and small gate pattern are facing each other along short gaps between them. And some parts of the gate patterns shown by some black points enclosed with the circle are burned by heat caused by the large amount of current through the semiconductor layer.
And, the current is generated by discharge between the gate patterns. In the burned points, some amounts of the semiconductor layer melt and then agglomerate or disappear by volatilization. Some amounts of gate insulation layer made of silicon dioxide also melt and then agglomerate or disappear by volatilization, which causes electrostatic destruction, the destruction of electric isolation. Thus, the transistor of this part does not work. Especially, if the transistor is one of the transistors which consist shift resister of peripheral circuit, signals cannot proceed to next shift resister and cannot be transferred to corresponding column or row. So, the whole next part of display panel cannot display any image.
FIG. 2
a
to
FIG. 2
d
show some states of process for making top gate type TFT in polycrystalline type LCD. In the figures, only a part of peripheral circuit region is shown schematically, upper part is area for p impurity type transistor and lower part is area for n impurity type transistor.
According to
FIG. 2
a
to
FIG. 2
d
, active regions
210
and
230
are formed. Then, gate patterns of varied shape
410
and
430
are formed. Ion implanting mask
50
made of photoresist is formed to cover active regions
210
of p type transistor area and n type ions are implanted for source/drain region
211
for n type transistor. Then, the ion implanting mask
50
is removed. Inversely, Ion implanting mask
60
is formed to cover active regions
230
of n type transistor region and p type ions are implanted for source/drain region
231
for p type transistor.
For the whole transistor to be operated punctually, ion implanting should be executed with equivalent conditions through the whole substrate. Generally, the result of examination shows that impurity ion concentrations in active regions of the same impurity type transistor area are equal over the whole substrate. Thus, the amount of implanted ions per standard area is equivalent over the substrate and it is thought that there is no reason for difference in electric potential among the gate patterns according to the sizes of the gate patterns. Nevertheless, the instant discharge between gate patterns happen and the reason for instant discharge is considered to be temporal unbalance of regional amount of implanted ions. To prevent the discharge between the gate patterns and destruction of transistor function, it is suggested that the gate patterns should be designed to have similar size. Actually, in case that the gate patterns are similar in size, the frequency of instant to discharge among neighboring gate patterns decrease. However, the adoption of such design method cause many confinement in device design works, which generate different types of problems concerning wiring.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of making TFT for display devices wherein instant discharge between conductor patterns in the process of ion implanting can be prevented.
It is another object of the present invention to provide a method of making TFT for display devices wherein destruction of electric isolation in the process of ion implanting with no change of pattern design can be prevented.
In order to achieve above mentioned objects and other objects of the present invention, a method of making TFT for display devices have the steps of forming subsidiary conductor patterns connecting plurality of electrically isolated conductor patterns, implanting impurity ions utilizing the conductor patterns and subsidiary conductor patterns as implantation mask and removing the subsidiary conductor patterns.
According to the present invention, in the process of making TFT, if the step of ion implanting should be executed more than once, it is most preferable to form subsidiary conductor pattern and remove it for each step of ion implanting. However, the frequency of the instant discharge differs according to ion source gas, types of ions, energy level or does level for implanting. For example, ion implanting mask made of metal having good conductivity more frequently cause instant discharge than ion implanting mask made of semiconductor does. And the instant discharge frequently happen where gaps between the conductor patterns are short and difference of area for the conductor patterns is large. So, it can be more effective to form subsidiary conductor pattern only for such ion implanting steps that cause more frequent instant discharge and only for conductor patterns where the gaps between the conductor patterns are short.
According to the present invention, if one subsidiary conductor pattern can be used for more than one step of ion implanting, there is no need for removing it, if possible, until the last step of the ion implanting. At this time, the subsidiary conductor pattern should be formed not to prevent ion implanting to active regions where impurity doping is needed. And after the target step of ion implanting, t

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