Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-03-17
2002-04-09
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S163000, C438S347000
Reexamination Certificate
active
06368903
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit devices using Field Effect Transistors (FETs), and more particularly, to a methods of making the same.
2. Description of Related Art
Conventional bulk silicon metal oxide semiconductor (MOS) and conductive metal oxide semiconductor (CMOS) technology has the ability to contact the silicon substrate from a relatively great distance away from a structure such as a field effect transistor (FET), e.g., 20-40 microns away, and hold the NFET body at ground potential. Likewise, contact with the n well of, for example, a PFET body may be made at a similar distance and be assured that it will be held at voltage (V
DD
). The device then has its own body voltage, and the on current/off current and overall circuit performance can be calculated with relatively great assurance. However, when designing and forming FETs on a silicon-on-insulator structure, where the device is formed over an insulating layer, the body tends to float relative to ground, and threshold voltage, on current, off current and other parameters are variable and not readily determined.
One attempt to solve this problem is shown in U.S. Pat. No. 5,821,575, the disclosure of which is hereby incorporated by reference. However, there remain problems with undesirable capacitance increases in body contact with the FET which remain unresolved by this proposed solution. Further problems are expected to occur when shallow trench isolation (STI) is applied to FETS on SOI.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an improved method and structure for making a FET on SOI.
A further object of the invention is to provide a method and structure for making an PET on SOI which reduces junction capacitance.
It is yet another object of the present invention to provide a reduced capacitance SOI FET which may be made using existing technology.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of making an FET device comprising providing a first dielectric layer with a substrate layer on the dielectric layer; forming a body contact region of a first conductivity type in the substrate layer; forming FET diffusion regions of a second conductivity type in the substrate layer; forming a channel region of the first conductivity type in the substrate, the channel region abutting the body contact region and separating the FET diffusion regions along edges of the FET diffusion regions, the first conductivity type material in the body contact region being thinner than the first conductivity type material in the channel region; depositing a gate above the substrate layer over the channel region; and depositing a second dielectric layer on the body contact region.
In a related aspect, the present invention provides a method of making an FET device comprising providing a first dielectric layer with a substrate layer on the dielectric layer; forming a body contact region of a first conductivity type in the substrate layer, the body contact region having an edge; forming FET diffusion regions of a second conductivity type in the substrate layer, the FET diffusion regions, the edge of the body contact region abutting only first edges of the FET diffusion regions; forming a channel region of the first conductivity type in the substrate, the channel region abutting the edge of the body contact region and separating the FET diffusion regions along second edges of the FET diffusion regions; depositing a gate above the substrate layer over the channel region; and depositing a second dielectric layer on the body contact region. Additionally, the method may include depositing at least one additional dielectric layer above both the FET diffusion regions and the second dielectric layer; forming first conductive contacts through the at least one additional dielectric layer for electrically contacting the FET diffusion regions; and forming a second conductive contact through the at least one additional dielectric layer and the second dielectric layer for electrically contacting the body contact region. Preferably, the body contact and channel regions are formed such that the first conductivity type material in the channel region is thicker than the first conductivity type material in the body contact region.
The forming of the body contact region may be made prior to forming the FET diffusion and channel regions, and the FET diffusion regions form source and drain regions of an FET. Preferably, the body contact, FET diffusion and channel regions are formed such that the body contact region extends continuously from the channel region and abuts both the FET diffusion regions only on at least a portion of the first edges of the FET diffusion regions. In one embodiment, the body contact, FET diffusion and channel regions are formed such that FET first edges are substantially perpendicular to the FET second edges, and the body contact region extends in a direction substantially perpendicular to the channel region. The body contact region may also extend outward from the channel region.
In another related aspect, the present invention provides a method of making an FET device comprising providing a first dielectric layer; depositing a substrate layer on the dielectric layer; forming a body contact region of a first conductivity type in the substrate layer, the body contact region having an edge; forming source and drain FET diffusion regions of a second conductivity type in the substrate layer, the FET diffusion regions, the edge of the body contact region abutting only first edges of the FET diffusion regions; and forming a channel region of the first conductivity type in the substrate having a thickness greater than that of the first conductivity type material in the body contact region. The channel region abuts the edge of the body contact region and separates the FET diffusion regions along second edges of the FET diffusion regions, with the body contact region extending continuously from the channel region and abutting both the FET diffusion regions only on a portion of the first edges of the FET diffusion region. The method also includes depositing a gate above the substrate layer over the channel region; and depositing a second dielectric layer on the body contact region. Preferably, the method further comprises depositing at least one additional dielectric layer above both the FET diffusion regions and the second dielectric layer; forming first conductive contacts through the at least one additional dielectric layer for electrically contacting the FET diffusion regions; and forming a second conductive contact through the at least one additional dielectric layer and the second dielectric layer for electrically contacting the body contact region. In one embodiment, the body contact, FET diffusion and channel regions are formed such that FET first edges are substantially perpendicular to the FET second edges, and the body contact region extends in a direction substantially perpendicular to the channel region.
A further aspect of the present invention relates to an FET device comprising a first dielectric layer; a substrate layer on the dielectric layer; a channel region of a first conductivity type formed in the substrate layer; a gate formed above the substrate layer over the channel region; FET diffusion regions of a second conductivity type formed in the substrate layer, the diffusion regions each having edges, the edges of the FET diffusion regions being separated by the channel region; a body contact region of the first conductivity type extending continuously from the channel region, the first conductivity type material in the body contact region being thinner than the first conductivity type materia
Bryant Andres
Mann Randy W.
Stamper Anthony K.
Chadurjian Mark F.
DeLio & Peterson LLC
International Business Machines - Corporation
Quach T. N.
Reynolds Kelly M.
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