Method of fabricating a semiconductor device

Details Method of fabricating a semiconductor device Method of fabricating a semiconductor device

2000-07-03

2002-01-15

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S637000, C438S702000, C438S740000

Reexamination Certificate

active

06339003

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating a semiconductor device which reduces leakage current by controlling an etch of a field oxide layer when a contact hole is formed.
2. Discussion of Related Art
As the integration of a semiconductor device increases, so the size of an unit transistor decreases. Thus, sizes of contact holes exposing impurity regions are reduced as well as the impurity regions for source and drain regions are decreased in size, causing difficulty in process. Besides, leakage current on the operation of the device is brought about by the etch of a field oxide layer due to misalignment in forming the contact holes.
Therefore, a technique of forming a borderless contact has been developed to reduce leakage current by forming the contact hole to be overlapped with a field oxide layer, which provides an easy process and prevents the etch of the field oxide layer.
FIG. 1A
to
FIG. 1D
show cross-sectional views of fabricating a semiconductor device according to a related art.
Referring to
FIG. 1A
, a field oxide layer
13
defining an active area and a field area of a device is formed on a p-typed semiconductor substrate
11
by shallow trench isolation(hereinafter abbreviated STI). In this case, the field oxide layer
13
is formed by forming a pad oxide layer(not shown in the drawing) and a mask layer(not shown in the drawing) which expose the field area on the semiconductor substrate
11
, by forming trenches
12
which are slant to a predetermined degree by carrying out an anisotropic etch such as reactive ion etching(hereinafter abbreviated RIE) and the like on the exposed parts of the semiconductor substrate
11
, by filling the trenches with silicon oxide, then by removing the pad oxide and mask layers.
After a gate oxide layer
15
has been formed on the active area of the semiconductor substrate
11
, polysilicon doped with impurities is deposited on the gate insulating layer
15
by chemical vapor deposition(hereinafter abbreviated CVD). Then, a gate
17
is formed by patterning the polysilicon to remain on a predetermined portion of the semiconductor substrate
11
by photolithography including anisotropic etches such as RME and the like.
Lightly doped regions
19
for LDD(lightly doped drain) regions are formed by implanting ions lightly into the exposed portions of the semiconductor substrate
11
with n typed impurities in use of the gate
17
as a mask.
Referring to
FIG. 1B
, a sidewall spacer
21
is formed at the sides of the gate
17
. In this case, the sidewall spacer
21
is formed by deposing silicon oxide on the semiconductor substrate
11
to cover the field oxide layer
13
and gate
17
by CVD, then by etching back the silicon oxide to have the semiconductor substrate
11
exposed by RIE.
Heavily doped regions
23
for a source and a drain region are formed by implanting with n typed impurity ions heavily into the exposed portions of the semiconductor substrate
11
in use of the gate
17
and sidewall spacer
21
as a mask.
Referring to
FIG. 1C
, a first insulating interlayer
25
is formed by depositing silicon nitride on the semiconductor substrate
11
to cover the field oxide layer
13
, gate
17
, and sidewall spacer
21
by CVD. And, a second insulating interlayer
27
is formed by depositing silicon oxide or BPSG(boro phospho silicate glass) on the first insulating interlayer
25
by CVD or by coating the first insulating layer
25
with SOG(spin on glass).
A first and a second contact hole
29
and
31
exposing the gate and heavily doped regions
23
respectively are formed by patterning the second and first insulating interlayers
27
and
25
by photolithography including anisotropic etch such as RIE and the like. As the thickness of the second insulating interlayer
27
is irregular due to the height difference between the gate
17
and heavily doped regions
23
, the first and second contact holes
29
and
31
are formed by etching the second insulating interlayer
27
sufficiently, which means that the second insulating interlayer
27
is overetched to expose the first insulating interlayer
25
corresponding to the heavily doped regions
23
, then by etching the first insulating interlayer
25
.
In this case, as the etch rate of the first insulating interlayer
25
is different from that of the second insulating interlayer
27
, the first insulating interlayer
25
as an etch stop layer prevents the field oxide layer
13
from being etched in spite of etching the second insulating interlayer
27
sufficiently.
Referring to
FIG. 1D
, an electrically-conductive substance such as polysilicon, Al, and the like is deposited on the second insulating interlayer
27
to be contacted with the gate
17
and heavily of doped regions
23
through the first and second contact holes
29
and
31
. Then, a first and a second plug
33
and
35
are formed in the first and second contact holes
29
and
31
respectively by removing the electrically-conductive substance to expose the surface of the second insulating interlayer
27
by chemical-mechanical polishing(hereinafter abbreviated CMP).
The above-mentioned method of fabricating a semiconductor device prevents the field oxide layer from being etched by overetching the second insulating interlayer to expose portions of the first insulating interlayer corresponding to the heavily doped regions for forming the first and second contact holes exposing the gate and heavily doped regions and by etching the first insulating interlayer successively.
Unfortunately, the method of fabricating a semiconductor device of the related art causes leakage current due to the difference in heat expansion coefficient between the semiconductor substrate and the first insulating interlayer of silicon nitride as well as stress caused by lattice mismatch.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of fabricating a semiconductor device that substantially obviates one or more of the proulenis due to limitations and disadvantages of the related art.
The object of the present invention is to provide a method of fabricating a semiconductor device which prevents the leakage current occurrence by avoiding the stress due to the contact between the semiconductor substrate and insulating interlayer.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes the steps of forming a field oxide layer defining an active area and a field area on a semiconductor substrate of a first conductive type, forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate, forming impurity regions of a second conductive type in the semiconductor substrate in use of the gate as a mask, forming a first insulating interlayer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate to cover the field oxide layer and the gate, forming a second insulating interlayer on the first insulating interlayer by depositing another insulator of which etch rate is different from that of the first insulating interlayer, forming a third insulating interlayer on the second insulating interlayer by depositing another insulator of which etch rate is different from that of the second insulating interlayer, and forming a first contact hole and second contact holes exposing the gate and heavily doped regions respectively by patterning the third to first

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