Method of forming a self-aligned contact pad for a...

Details Method of forming a self-aligned contact pad for a... Method of forming a self-aligned contact pad for a...

2000-08-24

2002-03-12

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S233000, C438S299000, C438S597000

Reexamination Certificate

active

06355547

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority from Korean Patent Application No. 99-35211 filed Aug. 24, 1999 with the Korean Industrial Property Office, which document is hereby incorporated by reference.
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device. More specifically, the present invention is directed to a method of forming a contact pad for a semiconductor structure with a high aspect ratio in the manufacture of a dynamic random access memory (DRAM).
BACKGROUND OF THE INVENTION
As the chip density of an integrated circuit increases, the minimum feature size shrinks down to a sub-half-micrometer regime. Accordingly, the margin of the lithographic alignment as well as the size of a contact that interconnects a conductive layer on the wafer has been reduced.
A self-aligned contact (SAC) technology has been proposed to solve the problems of the reduced alignment margin. U.S. Pat. No. 4,992,848 discloses a SAC technology that alleviates the burden of making a fine contact hole for a DRAM.
FIGS. 1A
to
1
E are schematic, cross-sectional views illustrating various manufacturing steps for implementing a traditional SAC pad. Referring to
FIG. 1A
, stacked gate structures each comprising a gate oxide
103
, a doped polysilicon layer
104
, a tungsten silicide
105
, and gate capping layers
106
and
107
are formed on the wafer with an active region
101
and a device isolation region
102
.
According to the prior art, the gate capping layers
106
and
107
are chosen to have an etch selectivity against an interlayer dielectric film to be formed in the subsequent processing step. Gate spacers
108
are formed on the sidewalls of the stacked gate structures using a material having an etch selectivity with respect to the interlayer dielectric film.
Referring to
FIG. 1B
, a first interlayer dielectric film is formed and then planarized by a chemical mechanical polishing (CMP) step to form a planarized dielectric film
110
. Thereafter, the prior art, as depicted in
FIG. 1C
, introduces an opening window
111
for a contact hole through lithography and the subsequent etching process.
Referring to
FIGS. 1D and 1E
, the SAC pads
113
,
114
, and
115
are completed by etching the conducting polysilicon layer
112
through the etch-back or the CMP process. However, as the chip density reaches the gigabit scale, shorts between the gate
104
,
105
and the contact pads
113
,
114
, and
115
could occur due to the reduced alignment margin in high-density DRAMs.
Furthermore, the horizontal dimension to be defined during the etching process is scaled down to a 0.1 &mgr;m regime while the vertical depth of the contact structure stays approximately in micrometer scale.
Accordingly, it is not easy to diffuse reactive gases into deep contact holes with a reduced diameter during a reactive ion etching (RIE) process to form SAC contacts. In addition, the drainage of the by-products during the RIE process is also difficult task for the fabrication of the deep-sub-half-micrometer devices.
As a result, an etching speed slows down during the RIE process for the formation of contact holes and the RIE process sometimes fails to complete the formation of contact holes due to the pile-up of the etch-stop products therein.
The RIE process is controlled in such a way that the etch-stop products, i.e. polymers, are minimized during the etching process. Further, the RIE etching time can also be prolonged. However, those schemes can result in shorts between the SAC pads
113
,
114
, and
115
and the gates
104
and
105
due to unwanted etching of the gate spacer
108
and the gate capping layers
106
and
107
.
In order to solve the above-mentioned problems, Y. Kohyama et. al proposed a new structure combining the bit line contact and the storage node in their paper entitled with, A fully printable, self-aligned, and planarized stacked capacitor DRAM cell technology for 1Gbit DRAM and beyond, pp.17-18, Technical Digest of Symposium on VLSI Technology, 1997.
The prior art of Y. Kohyama et. al, however, has a drawback of having a poor etch selectivity between the interlayer dielectric film
110
and the gate insulating layer or spacer
108
because the generation of the polymer is insufficient due to the relatively small surface area covered with the photoresist film.
It should be noted that the major path for a precursor, which contributes to the generation of the polymer, is both the injected gas and the photoresist film. Therefore, the amount of the supplied precursor is determined by the ratio of the surface area covered with the photoresist film.
Additionally, the prior art, as depicted in
FIGS. 1A
to
1
E, can not implement a gate spacer with a flat surface profile because the inner side of the tungsten silicide layer
105
on the polysilicon gate
104
is consumed.
As a result, voids can be created while the interlayer dielectric film is deposited for the formation of the SAC contact in accordance with the prior art.
Furthermore, leakage currents can flow if the device isolation region
102
is chemically attacked during wet etching. This is due to the loss of the silicon nitride layer that is supposed to function as an etch-stopper during the etching step of the interlayer dielectric film
110
.
In other words, the traditional methods for manufacturing SAC pads, as depicted in
FIG. 2
, has a problem in that the upper region
120
of a shallow trench isolation (STI) is vulnerable to a chemical attack during the wet etching. For instance, approximately 300 Å of the STI region can be consumed during the wet etching for the expansion of the SAC pad of the STI is 2500 Å.
Furthermore, referring to
FIG. 3
, SAC contact pads (not shown) can be electrically shorted to the gate stack
104
and
105
through a path
155
due to the loss of the active region
150
. This is because the etch-stopping silicon nitride layers, such as the gate capping layer
106
and the gate spacer
108
, can be lost during the wet-dipping process, following SAC contact holes forming step, to expand the SAC pad area.
Therefore, a need arises in the art for a method to manufacture SAC pads that are not subject to these limitations of the prior art.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of manufacturing SAC pads, which prevents shorts from occurring between gate structures and the SAC pads due to unwanted etching of gate spacers or of a gate-capping layer.
The present invention additionally provides a method of manufacturing SAC pads, which increases the alignment margin during lithography even for contact structures with a reduced dimension.
The present invention provides a method of manufacturing SAC pads, which makes it easy to separate the SAC pads during the etching process step.
Further, the present invention provides a method of manufacturing SAC pads, which prevents the generation of leakage currents in the device isolation region due to unwanted etching of the etch-stopping layer during etching of the interlayer dielectric film.
As a result, it becomes possible to form SAC contact pads without causing shorts and leakage problems of the prior art.
In accordance with the present invention, there is provided a method of manufacturing SAC pads. Firstly, a first insulating layer is formed over gate structures. Thereafter, a second insulating layer is formed on the first insulating layer and the second insulating layer sufficiently fills the spaces between the gate structures. Then contact holes are formed by etching the second insulating layer between the gate structures. Subsequently, a gate spacer is formed on the sidewalls of the gate structures by etching the first insulating layer and exposing the active region on the wafer. A first conductive layer is then deposited to completely fill the contact holes. Finally, the first conductive layer is separated through a step of etching the first conductive layer until the first insulating layer is exposed.


REFERENCES:
patent: 4728632

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