Method of manufacturing metal-oxide semiconductor transistor

Details Method of manufacturing metal-oxide semiconductor transistor Method of manufacturing metal-oxide semiconductor transistor

2002-03-13

2002-09-24

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S289000, C438S307000, C438S595000, C438S592000

Reexamination Certificate

active

06455388

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor.
2. Description of Related Art
The trend in the fabrication of very large scale integration (VLSI) circuits has always been to increase size of each silicon chip and decrease line width of devices and interconnects. Ultimately, more powerful functions may be provided by each silicon chip at a reduced cost. Moreover, a reduction in channel length of a transistor such as a metal-oxide-semiconductor (MOS) transistor also increases operating speed of the device.
However, as devices are miniaturized, a reduction in channel length often leads to an overlapping between the depletion layer around the source terminal and the drain terminal and the channel region. In general, the shorter the channel length, the greater will be the ratio of overlapping. With increasing channel length reduction, the effective length of a device channel is decreased, leading to the so-called short channel effect (SCE). To minimize the short channel effect, a shallow and lightly doped source/drain extension region is produced. Nevertheless, the incorporation of S/D extensions is incapable of preventing the high leakage current when the line width is smaller than 0.25 &mgr;m. A conventional method for reducing leakage current is to produce a doped pocket region at both ends of the channel close to the S/D extension region.
FIGS. 1A through 1C
are schematic cross-sectional views showing the progression of steps for fabricating a conventional metal-oxide-semiconductor transistor.
As shown in
FIG. 1A
, a substrate
100
having a gate electrode
102
thereon is provided. A light implantation
104
is carried out to form a source/drain extension region
106
in the substrate
100
.
As shown in
FIG. 1B
, a pocket implantation
108
is carried out to form a pocket region
110
in the substrate
100
under the side edges of the gate electrode
102
.
As shown in
FIG. 1C
, spacers
112
are formed on the sidewalls of the gate electrode
102
. Finally, a source/drain implantation
114
is carried out to form a source/drain region
116
in the substrate
100
on each side of the gate electrode
102
.
The aforementioned method of forming a MOS transistor is capable of preventing leakage current as line width is shortened to 0.25 &mgr;m or less. However, when line width is shortened to 0.13 &mgr;m or less, the pocket regions are so close to each other that another phenomenon called reverse short channel effect (RSCE) occurs. In RSCE, threshold voltage (Vt) suddenly shoots up, leading to device failure when the pocket distance is reduced beyond a certain value. In addition, the pocket regions are usually formed deep inside the substrate. Hence, overall minimization of short channel effect is quite limited.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of manufacturing a metal-oxide-semiconductor (MOS) transistor in a substrate. The method includes forming a pocket region at a shallow depth below the upper substrate surface under pre-defined pocket implantation conditions so that both short channel effect and reverse short channel effect are minimized. Hence, a deep sub-micron device can be fabricated.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating a MOS transistor. First, a substrate having a gate electrode and spacers on the gate electrode sidewalls is provided. A source/drain region is formed in the substrate outside the outer edge of the spacer sidewalls. A self-aligned silicide layer is formed over the exposed surface of the gate electrode and the source/drain regions. A portion of the spacers is removed by etching to form a sharp-angled spacer having a triangular cross-section on the sidewalls of the gate electrode. A pocket implantation of the substrate is carried out to form a pocket region inside the substrate under the side edges of the gate electrode. By controlling the energy level setting and the implant angle in the pocket implantation, a precise distribution of the dopants at desired locations within the substrate is reproduced. Hence, the pocket regions are formed close to the substrate surface. Finally, the sharp-angled spacers are removed and a light implantation is conducted to form source/drain extension regions in the substrate on each side of the gate electrode.
In this invention, sharp-angled spacers are used to reduce depth of ion implantation. Ultimately, the pocket regions are closer to the substrate surface and distance between the pocket region next to the source region and the pocket region next to the drain region is increased. Hence, both short-channel effect and reverse short channel effect are reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6046089 (2000-04-01), Gardner et al.
patent: 6211027 (2001-04-01), Lin et al.
patent: 6300205 (2001-10-01), Fulford et al.

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