Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-19
2002-03-12
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06355526
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device for storing information by accumulation of an electric charge and a method of manufacturing thereof. More specifically, the present invention relates to a non-volatile semiconductor memory device in which a memory element is selectively activated by a field effect transistor and a method of manufacturing thereof.
2. Description of the Prior Art
As a non-volatile semiconductor memory device having memory elements provided with floating gates and control gates, a flash memory can be mentioned as an example. A variety of designs are available for flash memories, one of which is a device in which a memory element is selectively activated by a field effect transistor. A flash memory with such a configuration has been disclosed, for example, in Japanese Patent Application Laid-Open No. 6-275847. In the following. a method of manufacturing the flash memory disclosed in the Japanese Patent Application Laid-Open No.6-275847 is described with reference to
FIGS. 23
to
31
.
As shown in
FIG. 23
, on a principal surface of a semiconductor substrate
200
, a silicon oxide layer
202
an a tunnel oxide layer is grown, and then a polysilicon layer
204
as a floating gate is formed. Part of the polysilicon layer
204
that is positioned over an access transistor formation region
232
is selectively etched an shown in
FIG. 24
, and remaining part of the polysilicon layer
204
positioned over a memory element formation region
234
is left. This remaining part of the polysilicon layer
204
is hereinafter referred to as a polysilicon layer
204
a
. As shown in
FIG. 25
, an ONO-layer
206
is formed on the polysilicon layer
204
a
, and a silicon oxide layer
208
as a gate oxide layer is formed over the access transistor formation region
232
. Subsequently, a polysilicon layer
210
is formed on the ONO-layer
206
and the silicon oxide layer
208
.
As shown in
FIG. 26
, a resist
212
is prepared on the polysilicon layer
210
which is then selectively etched by using the resist
212
as a mask, thereby forming a gate electrode
214
over the access transistor formation region
232
while leaving part of the polysilicon layer
210
that is positioned over the memory element formation region
234
. The remaining part of the polysilicon layer
210
over the memory element formation region
234
is hereinafter referred to as a polysilicon layer
210
a.
This etching exposes the silicon oxide layer
208
on a principal surface
236
of the semiconductor substrate
200
, in the area between the gate electrode
214
and a floating gate to be formed in a later step. Next, as shown in
FIG. 27
, the resist
212
is removed and a resist
216
in prepared over the memory element formation region
234
and the access transistor formation region
232
. The resist
216
is patterned so that it provides a mask for forming a control gate.
Note that the resist
216
is patterned so that it covers the gate electrode
214
, while at the same time its edge
216
a
does not overlap the polysilicon layers
204
a
and
210
a
. The gate electrode
214
has to be covered by resist
216
because the gate electrode
214
is formed of a material identical to that of the control gate and the floating gate, i.e. polysilicon, and therefore has to be protected from being etched away during the etching step to form the control gate and the floating gate. The patterning is provided in such a way that the edge
216
a
does not overlap the polysilicon layers
204
a
and
210
a
because when the polysilicon layers
204
a
and
210
a
are etched later to form the control gate and the floating gate, unnecessary polysilicon layers
204
a
and
210
a
are left on the principal surface of the semiconductor substrate
200
if the edge
216
a
overlaps the polysilicon layers
204
a
and
210
a
. Consequently, the resist
216
is patterned while being the silicon oxide layer
208
exposed on a principal surface
236
of the semiconductor substrate
200
, in the area between the gate electrode
214
and a floating gate to be formed in a later step.
The polysilicon layer
210
a
is selectively etched by using the resist
216
as a mask to form a control gate
219
. The ONO-layer
206
is then selectively etched by using the resist
216
as a mask, as shown in FIG.
29
. This etching removes the exposed portion of the silicon oxide layer
208
and exposes the principal surface
236
in the area between the gate electrode
214
and a floating gate to be formed in a later step.
As shown in
FIG. 29
, the polysilicon layer
204
a
is selectively etched by using the resist
216
as a mask, thereby forming a floating gate
220
. Since the principal surface
236
is exposed, the principal surface
236
is also etched to unavoidably form a groove section
222
on the principal surface
236
. Subsequently, an ion implantation is provided on the principal surface of the semiconductor substrate
200
by using the resist
216
as a mask, thereby forming a source/drain
224
in the memory element formation region
234
as well an an impurity region
226
electrically connected to the source/drain
224
, in the groove section
222
.
A silicon oxide layer
228
is grown on the principal surface of the semiconductor substrate
200
as shown in
FIG. 30
, followed by the formation of a contact hole
238
on the silicon oxide layer
228
so that the source/drain
224
is exposed. As shown in
FIG. 31
, an aluminum wiring
230
is then provided on the silicon oxide layer
228
. The aluminum wiring
230
is also formed on the contact hole
238
and is electrically connected to the source/drain
224
. A memory element
242
is provided with the control gate
218
, the floating gate
220
, and the source/drain
224
, whereas an access transistor
244
is provided with the gate electrode
214
and the source/drain
240
.
As described above, the control gate
218
and the gate electrode
214
have conventionally been prepared in separate steps. Consequently, there is a need to allow for a margin for aligning a mask for forming the control gate
218
and a mask for forming the gate electrode
214
, which has caused an obstacle for reducing the space between the control gate
218
and the gate electrode
214
.
SUMMARY OF THE INVENTION
The present invention has been made to eliminate the above-described problems with the prior art. Accordingly, an object of the present invention in to provide a non-volatile semiconductor memory device which can reduce the space between a control gate and a gate electrode and a method of manufacturing thereof.
According to one aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device that comprises:
a semiconductor substrate having a principal surface including a first region and a second region;
at least one memory element including a floating gate formed on the first region and a control gate formed on the floating gate; and
at least one access gate transistor for selectively activating the memory element, comprising a gate electrode formed on the second region.
This method comprises the steps of;
forming a tunnel insulation layer on the first region;
forming on the tunnel insulation layer a first conductive layer that functions as the floating gate;
forming a dielectric layer on the first conductive layer;
forming a gate insulation layer on the second region;
forming a second conductive layer on the dielectric layer and gate insulation layer;
forming on the second conductive layer a masking layer that has a different etching rate from the first conductive layer and functions as a mask when the first conductive layer is selectively etched;
selectively etching the masking layer and second conductive layer to simultaneously form the control gate and gate electrode, while leaving the masking layer on the control gate;
forming a first resist to cover the gate electrode; and
selectively etching the first conductive layer by using the mas
Booth Richard
Seiko Epson Corporation
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