Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-05-23
2002-05-21
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000, C438S589000
Reexamination Certificate
active
06391719
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the manufacture of semiconductor memory devices and more particularly to a method of manufacture of vertical FET devices formed in trenches in a semiconductor substrate and the devices formed thereby.
2. Description of Related Art
Currently, split gate flash memory devices have a misalignment problem and scaling down issues.
U.S. Pat. No. 5,108,938 of Solomon for “Method of Making a Trench Gate Complimentary Metal Oxide Semiconductor Transistor” shows a FET (Field Effect Transistor) with the source (S) and drain (D) regions on the substrate surface separated by a trench.
U.S. Pat. No. 5,391,506 of Tada et al. for “Manufacturing Method for Semiconductor Devices with Source/Drain Formed in Substrate Projection” shows a method for semiconductor devices with source/drain formed in substrate projection. A projection is formed in a substrate by anisotropic etching and a transistor is contained in the projection. The central portion of the projection covered with a gate electrode is formed as a channel region, and drain and source regions are formed on both sides of the projection by oblique ion implantation with the gate electrode as a mask. However, this reference differs from the configuration of the invention's split gate Flash with the source region at the bottom of the trench and the drain at the substrate surface.
U.S. Pat. No. 5,312,767 of Shimizu et al. for “MOS Type Field Effect Transistor and Manufacturing Method Thereof” shows a vertical SOI (Silicon On Insulator) transistor that has the source S and D regions on opposite ends of a trench. However the device is not a Flash memory.
U.S. Pat. No. 5,229,310 of Sivan “Method of Making a Self-Aligned Vertical Thin-Film Transistor in a Semiconductor Device” shows an EEPROM with a vertical orientation in a trench.
SUMMARY OF THE INVENTION
Objects of this invention are as follows:
1. Scaling down the size of split gate flash memory devices.
2. Providing devices without a misalignment issue for the polysilicon
1
layer and the polysilicon
2
mask.
3. The cell area can be compared with stacked gate flash memory.
A vertical, split gate, flash memory device in accordance with this invention has the features as follows:
1. Small cell area;
2. No misalignment;
3. high channel current.
In accordance with this invention a method is provided for forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thick floating gate layer of doped polysilicon over the tunnel oxide layer filling the trenches and extending above the trenches. Etch the floating gate layer down below the top of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thick control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes. Form spacers adjacent to the sidewalls of the control gate electrode.
REFERENCES:
patent: 5108938 (1992-04-01), Solomon
patent: 5229310 (1993-07-01), Sivan
patent: 5312767 (1994-05-01), Shimizu et al.
patent: 5391506 (1995-02-01), Tada et al.
patent: 5786612 (1998-07-01), Otani et al.
patent: 5998261 (1999-12-01), Hofmann et al.
patent: 6008089 (1999-12-01), Hong
patent: 6087222 (2000-07-01), Jung Lin et al.
patent: 6124608 (2000-09-01), Liu et al.
patent: 0485018 (1992-05-01), None
Chen Shui-Hung
Jung Lin Chrong
Kuo Di-Son
Ackerman Stephen B.
Chaudhuri Olik
Jones II Graham S.
Pham Hoai
Saile George O.
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