Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-09
2002-07-02
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S321000, C438S257000, C438S258000
Reexamination Certificate
active
06414351
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of computer memory circuits, and more specifically to a method for making reduced-size FLASH memory circuits, and to the resulting memory circuit.
BACKGROUND OF THE INVENTION
Electrically erasable and programmable read only memory (EEPROM) techniques also implement non-volatile memory on integrated circuits. EEPROMs can be electrically programmed, erased, and reprogrammed. EEPROM devices are useful as non-volatile memory units in computers and other systems. EEPROM circuits can also be used in chips whose primary function is not just memory, but includes other logical or computation functions. One technique of implementing an EEPROM is by use of a floating gate tunneling oxide (FLOTOX) transistor. To create a FLOTOX transistor, a field-effect transistor (FET) having source, drain, substrate, and gate terminals is modified to electrically isolate (float) the gate. This polycrystalline silicon (“polysilicon” or “poly”) floating gate is created over a thin insulating layer of silicon dioxide (tunnel oxide). A second polysilicon gate (control gate) is created above the floating gate. The floating gate and control gate are separated by an interpoly insulating layer. Since the floating gate is electrically isolated, any charge stored on the floating gate is trapped. Storing sufficient charge on the floating gate will create an inversion channel between source and drain of the FET. Thus, the presence or absence of charge on the floating gate can represent two distinct data values.
FLOTOX transistors are selectively programmed by transferring electronic charges through the thin gate oxide onto the floating gate by Fowler-Nordheim tunneling. With the substrate voltage held at ground, the control gate is raised to a sufficiently high positive voltage so that electrons are transferred from the substrate to the floating gate by tunneling through the insulating thin gate oxide. The tunneling process is reversible. The floating gate can be erased by grounding the control gate and raising the drain voltage to a sufficiently high positive voltage to transfer electrons out of the floating gate to the drain terminal of the transistor by tunneling through the insulating gate oxide. The voltage applied to the control gate during programming is higher than the voltage applied to the drain during erasure because, while the erasure voltage is applied directly across the gate oxide, the programming voltage is applied to the control gate and capacitively coupled onto the floating gate.
The transistors can be selectively reprogrammed in the same manner as described above, since the tunneling process is nondestructive. The programming and erasure voltages which effect Fowler-Nordheim tunneling are higher than the voltages normally used in reading the memory. The Fowler-Nordheim tunneling effect is negligible at the lower voltages used in reading the memory, allowing a FLOTOX transistor to maintain its programmed state for years if subjected only to normal read cycles.
Since reprogrammable non-volatile memory is useful for DRAM die identification and reconfiguring and remapping defective DRAM memory cells, it is desired to implement EEPROM through floating gate transistor structures which are compatible with existing DRAM processing steps.
U.S. Pat. No. 5,723,375 assigned to the assignee of the present invention (and incorporated herein by reference) describes a floating-gate memory cell that can be used in a DRAM or EEPROM.
Other convention fabrication techniques yield circuits having relatively large EEPROM memory cell areas. What is needed is a circuit which has an EEPROM memory cell area having a reduced area, and a method for producing such a circuit. What is also needed is a circuit having two or more different gate-oxide thicknesses, and a method for producing such a circuit.
SUMMARY OF THE INVENTION
The present invention provides an electronic circuit that includes a first set of one or more transistors each having a gate dielectric of a first thickness, and a second set of one or more transistors each having a gate dielectric of a second thickness different than the first thickness. In one embodiment, the circuit provides non-volatile EEPROM data storage.
In one embodiment, the first thickness is thicker than the second thickness. An initial thickness of dielectric is grown on both a first chip area for the first set of transistors and a second chip area for the second set of transistors. The dielectric is then removed from only the second chip area. Then a first and second final thickness of dielectric is grown on the first and second chip areas, respectively. Thus two distinct thicknesses of dielectric are provided.
In one such embodiment, the first and second chip areas are substantially co-planar. For example, a gate oxide is grown on a substrate to two distinct thicknesses.
In another such embodiment, the gate dielectric of the second thickness is an oxide layer sufficiently thin to allow Fowler-Nordheim tunneling for programming or erasing, and is covered by a polysilicon floating gate, a polysilicon control gate, and an electrical insulator layer separating the polysilicon floating gate and the polysilicon control gate. In one such embodiment, the gate dielectric of the first thickness is a gate oxide sufficiently thick to prevent electrical breakdown at operating voltages, and is covered by a polysilicon transistor gate that was deposited during the step that deposited the polysilicon floating gate.
One embodiment further includes a floating-gate poly layer over the second dielectric layer, an inter-poly nitride layer over the floating-gate poly layer, a control-gate poly layer over the inter-poly nitride layer, and a tungsten-silicide (WSix) layer over the control-gate poly layer.
In one such embodiment, the second dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer form a floating-gate stack on a silicon substrate. The stack is bounded by a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, and a drain end and a source end. The circuit further includes a nitride layer covering the first side from the inter-poly nitride layer to the first trench, a nitride layer covering the second side from the inter-poly nitride layer to the second trench, a nitride layer covering the drain end from the inter-poly nitride layer to the substrate, and a nitride layer covering the source end from the inter-poly nitride layer to the substrate.
Another embodiment further includes a tungsten drain contact formed substantially adjacent to the nitride layer covering the drain end, a tungsten source contact formed substantially adjacent to the nitride layer covering the source end, and a tungsten gate contact formed to substantially contact the WSix layer. In one such embodiment, an aluminum-copper (AlCu) line is formed substantially in contact with the tungsten drain contact.
Another aspect of the present invention provides a method for fabricating an electronic circuit. The method includes forming a first dielectric layer on both a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors, removing the first dielectric layer from the second chip area but not from the first chip area; and forming a second dielectric layer on both the first chip area to be used for the first set of transistors and on the second chip area to be used for the second set of transistors.
In one such embodiment, the first dielectric layer is thicker than the second dielectric layer, and wherein the first dielectric is a gate oxide for signal transistors, and the second dielectric is a gate oxide for memory-cell storage transistors. In another such embodiment, the first and second chip areas are substantially co-planar. In still another embodiment, the second dielectric layer is a gate oxide sufficiently thin to allow Fowler-Nordheim tunneling
Clampitt Darwin A.
Green James E.
Malsawma Lex H.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
Smith Matthew
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