Stepper alignment mark formation with dual field oxide process

Details Stepper alignment mark formation with dual field oxide process Stepper alignment mark formation with dual field oxide process

2001-04-16

2002-07-16

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S297000, C438S362000

Reexamination Certificate

active

06420224

ABSTRACT:

TECHNICAL FIELD
The present invention relates to integrated circuits and fabrication techniques for forming field oxide (FOX) regions on the integrated circuit substrate. More particularly, the present invention relates to fabrication techniques for improving the visibility of alignment marks used in forming dual field oxide regions on the integrated circuit substrate.
BACKGROUND OF THE INVENTION
Silicon dioxide (oxide) is a dielectric material widely used in the fabrication of integrated semiconductor circuits. The oxide thickness determines whether the oxide prevents shorting (insulator), or induction of electrical charges on the wafer surface. When used to prevent electrical charge induction from the metal layers, the oxide is referred to as a field oxide (FOX) layer. The magnitude of the voltages in the integrated circuit impacts the thickness of the FOX regions. By example, in fabricating a memory product, the core of the die is used to fabricate memory circuit elements, while the periphery is used for logic circuitry. Memory circuits operate at, or below, the 5.0 VDC range, while other circuitry, such as logic circuitry, operates in the 10 VDC to 20 VDC range. The higher voltages utilized in the periphery requires a thicker FOX than the FOX used in the core of the die (4000 Å compared to 2000 Å). In order to fabricate the die with the two thicknesses of FOX in the core and periphery areas of the die, a dual FOX layering process must be employed.
As is known in the prior art, masks are provided with an alignment mark for use in aligning the various patterns on the wafer. A first mask creates a target on the wafer at a first patterning step. Subsequent masks contain masks portions which align to the previously formed mask. In dual field oxide fabrication processes, the second masking operation has traditionally caused a second layer of oxide material to be fabricated over the previously fabricated alignment marker. The subsequent alignment after the dual field oxide process has caused misalignment problems and device failures. Any attempts to test for mask misalignment is frustrated because of the second layer of oxide material that has been fabricated over the previously fabricated alignment marker. Thus, a need is seen to exist for a fabrication process involving dual field oxide fabrication where the alignment marker is not diminished by the second field oxide layer and that facilitates checking for mask misalignment during subsequent masking operations.
Accordingly, a primary object of the present invention is to provide a [photomask] mask set that produces an alignment mark that is accurate for subsequent fabrication process after undergoing a dual field oxide (FOX) fabrication process.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the foregoing object is accomplished by providing a semiconductor mask set for producing wafer alignment accuracy in a semiconductor fabrication process. The mask set produces an alignment mark that is accurate for subsequent fabrication after undergoing a dual field oxide (FOX) fabrication process. Prior art methods have traditionally covered the alignment marks with layers of oxide material. The present method includes the steps of: (a) providing a first mask member having mask portions for forming a plurality of first field oxide regions on a first region of a semiconductor substrate and also having a mask portion for forming an alignment marker; (b) providing a second mask member having mask portions for forming a plurality of second field oxide regions on a second region of the semiconductor substrate and also having mask portions delineated for covering any first field oxide regions and alignment marker formed by using the first mask member; (c) forming the first field oxide regions and the alignment marker utilizing the first mask member; (d) covering the formed first field oxide regions and the alignment marker with a photoresist material by utilizing the second mask member; (e) forming the second field oxide regions after utilizing the second mask member; (f) facilitating wafer alignment accuracy by removing the photoresist material and exposing the alignment marker; and (g) aligning a semiconductor wafer by utilizing the exposed alignment marker. The mask set can be used in conjunction with stepper wafer alignment tools and is especially useful in forming a memory semiconductor product capable of performing block data erasure operations. Additionally, the exposed alignment marker resulting after the second field oxide facilitates testing for mask misalignment during subsequent masking operations.
Other features of the present invention are disclosed or apparent in the section entitled: “DETAILED DESCRIPTION OF THE INVENTION.”


REFERENCES:
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patent: 5966618 (1999-10-01), Sun et al.
patent: 360063921 (1985-04-01), None
patent: 3049212 (1991-03-01), None
Wolf et al., “Silicon Processing for the VLSI Era,” 1986, pp. 471-476.

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