Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-02-28
2002-05-07
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S913000, C438S795000, C438S781000
Reexamination Certificate
active
06383927
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a fabrication technology for a semiconductor device and, more particularly, to a process for fabricating a semiconductor device, a fabrication apparatus used therein and a method for entering a semiconductor wafer into the fabrication apparatus.
DESCRIPTION OF THE RELATED ART
An integrated circuit has been complicated, and the manufacturer is required to integrate a large number circuit components on a small semiconductor chip. The circuit component such as a field effect transistor is miniaturized, and the miniature field effect transistor requires an extremely thin gate oxide layer. When the manufacturer designs a field effect transistor under 0.25 micron design rules, the gate oxide layer is of the order of 8 nanometers thick. Now, the manufacturers are targeting a gate oxide layer of 5 nanometers thick or less.
Typical examples of oxidation technology are written in “Apparatus Technologies for Realizing Gate Oxide Equal to or Less Than 5 nm (DSI)”, monthly magazine “Semiconductor World”, July 1996, pages 103 to 108. Silicon wafers are inserted into a quartz boat, and the quartz boat is inserted into a furnace. The furnace chamber is purged with nitrogen, and residual oxygen at the entrance for the boat is of the order of 2 to 3 percent. However, natural oxide is grown to 10 to 20 angstroms thick on the silicon wafers in the furnace chamber at 800 degrees in centigrade. The nitrogen is smaller in molecular weight than the air, and hardly pushes out the air from the gaps between the silicon wafers. In other words, the air is hardly evacuated from the gaps between the silicon wafers.
The article proposes several apparatus against undesirable growth of natural oxide. One of the apparatus against the undesirable oxidation is a load-lock chamber provided under an entrance of a vertical oxidation diffusion furnace, and nitrogen gas flows across the gap between the load-lock chamber and the entrance of the furnace chamber. A lifter is installed in the load-lock chamber, and a boat is mounted on the lifter. The lifter is upwardly moved, and inserts the board into the furnace chamber. The nitrogen gas is expected to blow the air off.
Another apparatus is a nitrogen purge box attached to the furnace entrance. The boat is placed in the nitrogen purge box before the entry into the furnace chamber, and a large amount of nitrogen is blown into the nitrogen purge box. The nitrogen is expected to enter into the gaps between the silicon wafers, and the residual air is replaced with the nitrogen.
Yet another apparatus is a double wall furnace. The boat is inserted into the inner tube, and the nitrogen gas is blown into the inner tube. The air between the silicon wafers is replaced with the nitrogen. The inner tube is inserted into the outer tube, and the silicon wafer is heated.
The load-lock chamber and the nitrogen purge box are attached to a conventional furnace, and the manufacturer requires cost for remodeling the furnace. The double wall furnace is complicated, and is expensive. In any case, the manufacturer requires large cost for replacing the conventional furnace with the double wall furnace. Thus, the apparatus proposed in the article are not economical.
A prior art lateral oxidation diffusion furnace is proposed in Japanese Patent Publication of Unexamined Application No. 4-162526. The Japanese Patent Publication of Unexamined Application proposes to use inert gas larger in molecular weight than nitrogen for the inert gas purge. Argon is the inert gas larger in molecular weight than the nitrogen.
FIG. 1
illustrates a typical example of the vertical oxidation diffusion furnace, and the inert gas purge disclosed in the Japanese Patent Publication is applied to the vertical oxidation diffusion furnace. The prior art vertical oxidation diffusion furnace largely comprises a quartz tube
1
, a lifter
2
and a quartz boat
3
. The quartz tube
1
defines a furnace chamber
1
a,
and has an entrance
1
b
open to the atmosphere at the lower end thereof. The lifter
2
includes a table
2
a
and a drive mechanism
2
b,
and the table
2
a
is aligned with the entrance
1
b.
The driving mechanism
2
b
upwardly moves the table
2
a
and the vice versa, and the entrance
1
b
is closed by the table
2
a.
A warmer
4
is placed on the table
2
a,
and the quartz boat
3
is stacked on the warmer
4
. A gas nozzle
5
and a gas exit
6
are provided to the quartz tube
1
around the entrance
1
b.
The gas nozzle
5
is connected to an argon gas source (not shown), and the gas exit
6
is connected to a vacuum source.
A manufacturer oxidizes silicon wafers
7
or diffuses dopant impurity into the silicon wafers
7
as follows. The driving mechanism
2
b
moves the table
2
a
to the lower limit, and the entrance
1
b
becomes open to the atmosphere. The silicon wafers
7
are inserted into the quartz boat
3
, and the quartz boat
3
is placed on the warmer
4
. The driving mechanism
2
b
upwardly moves the table
2
a,
and the quartz boat
3
is inserted into the furnace chamber
1
a.
The entrance
1
b
is closed. The argon gas is introduced from the gas nozzle
5
into the furnace chamber
1
a,
and is exhausted from the furnace chamber through the gas exit
6
. Thus, the air is gradually evacuated from the furnace chamber
1
a,
and is replaced with the argon gas.
FIG. 2
illustrates another prior art vertical oxidation diffusion furnace. The difference from the prior art vertical oxidation diffusion furnace shown in
FIG. 1
is the location of the gas nozzle
5
, and components of the vertical oxidation diffusion furnace are labeled with the same references designating corresponding components of the prior art vertical oxidation diffusion furnace shown in FIG.
1
.
The argon gas is larger in molecular weight than the air and the oxygen, and is expected to push out the residual oxygen from the gaps between the silicon wafers
7
. However, a problem is encountered in the prior art furnaces in that the residual air is left in the furnace chamber, and the silicon wafers
7
are undesirably oxidized by the oxygen of the residual air.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a process for fabricating a semiconductor device, in which oxidation of a semiconductor wafer is precisely controlled without cost.
It is also an important object of the present invention to provide an apparatus for precisely controlling the oxidation of the semiconductor wafer.
It is also an important object of the present invention to provide a method for entering a semiconductor wafer into the apparatus.
The present inventor contemplated the problem inherent in the prior art, and noticed that the argon gas got under the residual air in the furnace chamber. The boat
3
is upwardly protected from the entrance
1
b.
Although the air was gradually replaced with the argon gas, the air was hardly evacuated from the upper portion of the furnace chamber
1
a,
and the residual air oxidized the silicon wafer at a higher level. The present inventor measured the residual oxygen in the furnace chamber
1
a,
and the oxygen concentration was greater than that in the prior art load-lock chamber, i.e., 10 ppm to 50 ppm. Thus, there was a trade-off between the inert gas lighter than the air and the inert gas heavier than the air. The present inventor concluded to share the evacuation work between different kinds of inert gas.
To accomplish the object, the present invention proposes to use gaseous mixture between a first kind of inert gas lighter than the oxygen and a second kind of inert gas heavier than the oxygen for the evacuation work.
In accordance with one aspect of the present invention, there is provided a process for fabricating a semiconductor device comprising the steps of preparing a semiconductor wafer having a portion of a first material reactive with oxygen, supplying a first purge gas less reactive with the first material and smaller in molecular weight than the oxygen and a second purge gas less reactive with
Bowers Charles
McGinn & Gibb PLLC
NEC Corporation
Nguyen Thanh
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