Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-08-11
2002-09-03
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C365S201000
Reexamination Certificate
active
06446228
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit testing apparatus for testing a semiconductor integrated circuit, and more particularly, relates to a semiconductor integrated circuit testing apparatus (generally referred to as IC tester) which can be suitably used in testing a semiconductor integrated circuit having a logic portion and a memory portion formed together on one chip, and to a method of controlling the semiconductor integrated circuit testing apparatus, which defines the sequence of operations of the testing apparatus.
2. Description of the Related Art
Heretofore, a semiconductor integrated circuit (hereinafter referred to as IC) is called, in this technical field, a memory IC or a logic IC. The memory IC is one in which a memory portion is dominant therein, and the logic IC is one in which a logical circuit portion (logic portion) is dominant therein. In addition, an IC having a logic portion and a memory portion formed together on one chip (also referred to as logic/memory mixed IC) is called a systematic LSI (Systematic Large Scale Integrated Circuit) or the like, and the ICs of this type tend to increase from now on. The characteristic of a systematic LSI is that the number of pins required for a logic portion is several times or so as large as the number of pins required for a memory portion. Therefore, in the case of testing a logic portion of such a systematic LSI, the number of ICs that can be simultaneously tested (commonly called the number of ICs to be simultaneously measured or the number of parallel measurements) is limited due to the large number of pins of the IC under test.
FIG. 7
shows a connecting relationship between an IC testing apparatus and ICs under test (hereinafter, referred to as DUTs) in the case that the DUTs are ICs each having a logic portion and a memory portion formed together on one chip. There are provided in the IC testing apparatus
10
many channels (signal paths) through which driving signals (test pattern signals, address signals, control signals and the like) are supplied to the DUTs. The number of DUTs to be simultaneously tested is determined depending on the total number of channels.
FIG. 7
is a block diagram showing, by way of example, a connecting state in the case of testing two DUTs (DUT
1
and DUT
2
) each having 256 pins by the IC testing apparatus
10
having total of 512 channels CH
1
through CH
512
that are channel
1
(CH
1
) through channel
512
(CH
512
). Each of the DUT
1
and the DUT
2
is assumed to be a logic/memory mixed IC having 64 pins from pin P
1
until pin P
64
as the pins for testing the memory portion, and 192 pins from pin P
65
until pin P
256
as the pins for testing logic portion.
In this case, 64 channels
11
from channel CH
1
until channel CH
64
of the IC testing apparatus
10
are connected to the pins P
1
through P
64
of the DUT
1
, respectively, and the 192 channels from channel CH
65
through channel CH
256
of the IC testing apparatus
10
are connected to the pins P
65
through P
256
of the DUT
1
, respectively. However in this case, since the memory portion must be also operated for testing the logic portion of the DUT
1
, each of 256 channels
12
from channel CH
1
through channel CH
512
of the IC testing apparatus
10
is connected to corresponding one of the pins P
1
through P
256
of the DUT
1
to perform the testing. Since the connecting relationship for the DUT
2
is quite similar to the case of the DUT
1
, the explanation thereof will be omitted.
In this manner, since only two DUTs can be connected to the IC testing apparatus
10
under the above conditions, as shown in
FIG. 7
, two DUTs, namely, DUT
1
and DUT
2
are connected to the IC testing apparatus
10
, and the logic portion and the memory portion of each of the DUT
1
and the DUT
2
are tested to determine whether they have any defect or not.
Incidentally, although the required number of pins of the memory portion is less than that of the logic portion, there is a characteristic that a time duration or length Mt required for testing the memory portion is longer than a time duration or length Lt required for testing the logic portion. For example, in the case of the DUTs
1
and
2
shown in
FIG. 7
, Mt is 60 seconds, while Lt is approximately 5 seconds or so. Therefore, in this case, it takes approximately 65 seconds for testing both of the logic portion and the memory portion. For example, in the case of testing 1000 DUTs of this type, the required time length for the testing is, as two DUTs can be connected to the IC tester
10
at the same time, (60+5)×1000×256/512=65×1000×1/2=32500 seconds≈9 hours.
This value of 9 hours is a time length required for the test only, and in reality, there is necessary, in addition to the test, a sorting process for sorting the tested ICs into non-defective articles and defective articles is necessary. Therefore, the time length required for the sorting process must be added. Consequently, a longer test time is actually required. Further, assuming that the number of channels to be used for testing the logic portion of a DUT is Lch, and the total number of channels of the IC tester
10
is Tch, “256/512” in the above calculating formula corresponds to Lch/Tch. This is equal to the reciprocal of the number of DUTs that can be tested simultaneously.
As mentioned above, when ICs of mixed logic/memory are tested by one IC testing apparatus, there is a problem that the time length required for testing the ICs becomes long. For this reason, there may be employed a case that two IC testing apparatus are provided for testing the memory portions of the ICs of mixed logic/memory using one of the two IC testing apparatus, and for testing the logic portions of the ICs of mixed logic/memory using the other one of the two IC testing apparatus.
FIG. 8
shows a connecting relationship between an IC testing apparatus
10
and DUTs in the case that the only memory portions of the logic/memory mixed ICs are tested by the IC testing apparatus
10
shown in FIG.
7
. In the case of testing the memory portions of the DUTs, it is sufficient that the IC testing apparatus
10
supplies the driving signals only to the pins for the memory portion of each DUT. As already explained with reference to
FIG. 7
, the total number of channels Tch of the IC testing apparatus
10
is 512, and the number of pins required for the memory portion of each DUT is 64 pins from P
1
to P
64
. Therefore, 512/64=8 DUTs (DUT
1
, DUT
2
, DUT
3
, . . . , DUT
8
) can be connected to the IC testing apparatus
10
. Consequently, the number of DUTs that can be connected to one IC testing apparatus is remarkably increased.
In this manner, in the case of testing the memory portion, the number of DUTs that can be simultaneously tested is eight.
Therefore, the time length required for testing, for example, 1000 DUTs is 60×1000×64/512=7500 seconds. In this case, assuming that the number of channels to be used for testing the memory portion of a DUT is Mch, “64/512” corresponds to Mch/Tch. This is equivalent to the reciprocal of the number of DUTs that can be simultaneously tested.
When the logic portions of the 1000 DUTs are tested by the other one of the two IC testing apparatus (the connecting relationship is the same as that shown in FIG.
7
), the test time duration is 5×1000×256/512=2500 seconds. As a result, when the memory portions and the logic portions of the DUTs are separately tested by two IC testing apparatus, respectively, the total time length Ttim required for the test is 7500 seconds+2500 seconds=10000 seconds. When this time length is compared with the time length (32500 seconds) required in the test by one IC testing apparatus, it is recognized that there is an advantage in the two IC testing apparatus case that the required time length can be remarkably reduced. However, in this case, also the sorting process is necessa
Advantest Corporation
De'cady Albert
Gallagher & Lathrop
Lathrop David N.
Torres Joseph D.
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