Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-01-10
2002-05-07
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S638000, C438S672000
Reexamination Certificate
active
06383920
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the manufacture of semiconductor devices, and more particularly to a method of enclosing a metal via in a dual damascene process.
BACKGROUND OF THE INVENTION
Damascene processes are widely used in the manufacture of semiconductor devices. Generally, in a damascene process, a dielectric layer is first deposited on a substrate, a portion of the dielectric layer is then removed by an etching process in accordance with a mask pattern, the etched areas in the dielectric layer are lined with a barrier metal and then filled with a metal, and finally the excess liner and metal deposited over the dielectric layer is removed in a planarization process. By this method, metal features such as vias or lines are formed on a substrate.
Typically, vias and lines are formed in separate damascene processes, known as single damascene. For example, to form a layer of metal lines on a substrate, a dielectric layer is first deposited, then a portion of the dielectric layer is etched according to a mask pattern which corresponds to the desired line pattern, a metal liner is then deposited on the dielectric layer and in the etched line areas in the dielectric layer, these etched line areas are then filled with a metal, and finally the excess metal and liner on top of the dielectric layer is removed in a planarization process. A layer of vias are formed in a similar process, except that the mask pattern corresponds to the desired via pattern. Thus, to form a layer of vias and lines, two metal fill steps and two metal planarization steps are required.
In the electronics industry, there is a current trend toward using more cost effective dual damascene in the fabrication of interconnection structures. In a dual damascene process, both the via and the line are formed in the same damascene process. To form the via and the line in the same damascene process, a thicker dielectric layer is first deposited on a substrate, the dielectric layer is then etched according to a mask pattern which corresponds to both the desired via pattern and the desired line pattern, a liner is then deposited on the dielectric layer and in the etched areas in the dielectric layer, these etched areas are then filled with a metal, and the excess metal and liner is removed by a planarization process. This dual damascene process therefore reduces the number of costly metal fill and planarization steps.
However, recent studies have shown that interconnection structures formed using a dual damascene process are susceptible to failure caused by electromigration effects.
FIG. 1
illustrates a cross sectional view of a wafer stack
100
formed using a conventional dual damascene process. The wafer stack
100
includes a substrate
102
, an oxide layer
104
, a metal layer
106
, a dielectric layer
108
, a liner
110
, a metal via
112
and a metal line
114
. The metal via
112
and metal line
114
are formed by a dual damascene process in which the dielectric layer
108
is first deposited on top of the metal layer
106
, the dielectric layer
108
is then etched to form via
112
and trench
114
according to a mask pattern which defines the desired line and via pattern, the liner
110
is deposited on the dielectric layer
108
and in the etched portions of the dielectric layer
108
, a metal is then deposited in the via
112
and trench
114
, and finally the excess metal and liner on top of the dielectric layer
108
are removed by a planarization process.
In this wafer stack configuration, when an electric potential is applied across the metal via
112
and metal line
114
, the electric potential causes an electromigration effect in the metal via
112
and metal line
114
. Specifically, the electric potential causes one portion of the interconnect structure to be a cathode and the other portion to an anode. The electric potential between the cathode and the anode causes a current flow from the anode end to the cathode end through metal via
112
and metal line
114
. Since the direction of electrons is opposite of the direction of current flow, the electrons migrate from the cathode end of the metal via
112
toward the anode end of the metal line
114
. In this process, the moving electrons generate an “electron wind” which pushes or forces the metal atoms in the direction of the electrons from the metal via
112
near the cathode to the metal line
114
near the anode. The liner
110
prevents the electrons and atoms in the metal layer
106
from migrating to the metal via
112
and metal line
114
. As a result, a void
116
forms near the cathode in the metal via
112
. The formation of this void often leads to catastrophic failure of the device. The failure is catastrophic because the liner
110
at the bottom of the via
112
is often thinner than in the line and therefore is unable to shunt the current across the void.
Void formation due to electromigration is a well known phenomenon. Several methods have been proposed to counteract this electromigration effect in interconnects and thereby prevent void formation. For example, in IBM Technical Disclosure Bulletin Vol. 31, No. 6 (1988), tungsten (W) links are interposed periodically in long aluminum-copper (Al-Cu) lines or minimum groundrule features interfacing contact pads. These tungsten links form a physical barrier to the Al-Cu atoms being transported between the cathode to the anode. As another example, U.S. Pat. No. 5,470,788 to Biery et al. proposes interposing segments of Al with segments of refractory metal such as W.
Each of these methods utilize the “short-length effect.” The short-length effect takes place in short interconnections if an electrical current is supplied through leads of materials in which the diffusivity of the interconnection metal is low. The physical origin of the short-length effect is the build-up of backstress. As interconnection metal atoms pile up against the diffusion barrier leads, this backstress counteracts the electromigration driving force. A steady-state condition arises in situations where the backstress exactly balances the electromigration driving force. Under this condition, no further electromigration damage occurs.
The existence of the short-length effect has been demonstrated by several investigators, such as by H. V. Schreiber in the article “Electromigration Threshold of Aluminum Films” published in Solid State Electronics, Vol. 28, No. 6, p. 617; by R. G. Filippi et al., in the article “Evidence of the Electromigration Short-Length Effect in Aluminum Based Metallurgy with Tungsten Diffusion Barriers” published in the Proceedings of the Materials Research Symposium, Vol. 309, pp. 141-148,; and by X. X. Li et al., in the article “Increase in Electromigration Resistance by Enhancing Backflow Effect” published in the Proceedings of the 30th International Reliability Physics Symposium, March
1992
, p. 211.
The short-length effect has been used advantageously to reduce the electromigration effect in via-line interconnects by enclosing or encapsulating the via. For example, U.S. Pat. No. 6,054,378 to Skala et al. (“Skala”) discloses a method for encapsulating a metal via in a damascene process. The encapsulation of the metal via with a conductive barrier layer prevents the electromigration of interconnect metal atoms from the via to the line and thereby prevents voiding at the bottom of the via.
Although the method disclosed in the Skala patent is described as a dual damascene process, an examination of the process steps reveals that the via and line actually are formed in two single damascene processes. Referring to
FIGS. 2A-2I
of Skala, the via is formed, encapsulated, filled and planarized in the single damascene process depicted in
FIGS. 2B-2E
. Then the trench is formed, encapsulated, filled and planarized in a second single damascene process depicted in
FIGS. 2F-2I
. As discussed previously, a dual damascene process is more cost effective because the metal fill and planarization steps are performed only once. Therefore, there is a need in the art for
Edwards Robert D.
Filippi Ronald G.
Iggulden Roy C.
Kiewra Edward W.
Wang Ping-Chuan
Brewster William M.
Dang Trung
International Business Machines - Corporation
Pepper Margaret A.
LandOfFree
Process of enclosing via for improved reliability in dual... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process of enclosing via for improved reliability in dual..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process of enclosing via for improved reliability in dual... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2835915