Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-04
2002-04-16
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S138000, C438S981000, C438S589000
Reexamination Certificate
active
06372579
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process of producing a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor, particularly to a method of producing an LDMOS transistor having reduced dimensions, reduced leakage, and a reduced propensity to latch-up.
2. Description of the Prior Art
The Laterally Diffused Metal-Oxide Semiconductor (LDMOS) usually used in the high-voltage integrated circuits may generally be manufactured using some of the same techniques used to fabricate the low voltage circuitry or logic circuitry. Hence, a commonly used high-voltage element for these circuits is the laterally diffused Metal-Oxide transistor (LDMOS). It is firstly mentioned that conventional LDMOS structures are part of the basic understanding.
SUMMARY OF THE INVENTION
The present invention provides a method for forming a laterally diffused metal oxide semiconductor transistor. The method comprises following steps. First, a P substrate is provided. Then, a first N-well and a first P-well are formed and separated from each other in the P substrate, wherein the first N-well and the first P-well are not adjacent to each other. Next, a second N-well and a second P-well are formed and separated from each other in the P substrate, wherein the second N-well overlies the first N-well and the second P-well overlies the first P-well. Thereafter, a field oxide region is formed in the P substrate between the first N-well and the first P-well and the field oxide region overlies on a portion of the second N-well and a portion of the second P-well. Then, a trench is formed in the P substrate by removing a portion of the field oxide region and a portion of the P substrate, wherein the remained field oxide region only overlies on the second N-well. Next, a gate oxide layer is formed on a bottom surface and a sidewall of the trench and on a surface of the second P-well in the P substrate. Thereafter, a polysilicon gate is formed on the P substrate, wherein the trench is filled with the polysilicon gate and the polysilicon gate overlies on a portion of the remained field oxide region and a portion of the second P-well. Next, a N
+
-type source/drain is formed in the P substrate, wherein the N
+
-type source/drain is adjacent to the trench and overlies the second P-well, and adjacent to the remained field oxide region and overlies the second N-well. Last, a P
+
-type drain is formed in the P substrate, wherein the P
+
-type drain is adjacent to the N
+
-type source/drain and overlies the second P-well.
The deep portion and the lightly doped portion are formed simultaneously. Also the deep portion and the lightly doped portion are formed simultaneously by implanting dopants of the conductivity type. Then a lightly doped portion of the second drain/source region is formed bordering said channel is carried out.
REFERENCES:
patent: 4691433 (1987-09-01), Pimbley et al.
patent: 4721987 (1988-01-01), Baglee et al.
patent: 5506431 (1996-04-01), Thomas
patent: 5723891 (1998-03-01), Malhi
Trinh Michael
United Microelectronics Corp.
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