Two chamber metal reflow process

Details Two chamber metal reflow process Two chamber metal reflow process

1997-12-23

2002-04-02

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S688000, C438S627000, C438S643000, C438S637000, C438S672000

Reexamination Certificate

active

06365514

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of semiconductor devices, and more specifically, to a process for forming aluminum alloy plugs in the fabrication of semiconductor devices.
2. Background Information
As semiconductor devices become smaller so must the conductive contacts, plugs, vias, and interconnect lines of those devices. Tungsten (W) plug technology is widely used in the fabrication of semiconductor devices. However, tungsten plug technology entails the use of expensive equipment and a large number of processing steps.
A low cost alternative to tungsten plug technology is the use of aluminum (Al) and aluminum alloys to fill plugs. Additionally, because aluminum can be sputter deposited and reflowed into the plug, it results in a metallization scheme with a significant reduction in the number of processing steps. However, as the dimensions of the vias decrease to less than 0.5 micron (&mgr;) in new generations of semiconductor devices, current methods for filling plugs with aluminum are also subject to the formation of holes or voids.
FIGS. 1
a
through
1
c
illustrate the problems associated with filling small openings in a semiconductor wafer using prior art methods of reflowing aluminum and aluminum alloys.
FIG. 1
a
illustrates a cross-sectional view of a semiconductor wafer (wafer) having a dielectric layer
120
formed over a substrate
110
. Opening
130
may be formed in dielectric layer
120
using standard photoresist and etch techniques.
A wetting layer
140
, for example titanium (Ti), is deposited over the wafer and lines the sidewalls and bottom of opening
130
. Wetting layer
140
helps to reduce the interfacial energy between the aluminum that is to be deposited and substrate
110
and/or dielectric layer
120
. Wetting layer
140
also helps to reduce or avoid agglomeration between the aluminum that is to be deposited and substrate
110
and/or dielectric layer
120
.
Typical prior art methods deposit the aluminum in two steps, a cold deposition step followed by a hot deposition step. In one prior art method an aluminum layer
160
is sputter deposited over wetting layer
140
during the cold deposition step and is reflowed into opening
130
during the hot deposition step, as is illustrated in
FIG. 1
b
. At the relatively higher temperature for reflow, however, aluminum (Al) layer
160
reacts with titanium (Ti) wetting layer
140
and forms intermetallic (TiAl
3
) compound layer
150
. It should be noted however, that not all of aluminum layer
160
will react with titanium wetting layer
140
to form intermetallic (TiAl
3
) compound layer
150
. As soon as all the available titanium in titanium wetting layer
140
has reacted to form TiAl
3
, the remaining aluminum being deposited forms aluminum layer
160
and the aluminum (Al) plug
165
.
FIG. 1
c
illustrates a cross-sectional view of a semiconductor wafer after opening
130
has been completely filled with aluminum.
One of the problems with using a cold and a hot deposition step is that the overhang of the low temperature aluminum layer tends to close or “pinch” the top of the opening, especially in small vias (i.e. less than 0.5 micron (&mgr;)), as is illustrated in
FIG. 1
b
. Consequently, as is illustrated in
FIG. 1
c
, the migration of aluminum (Al) into the opening during the high temperature aluminum fill may slow down, and cause a hole or void
170
to form in the plug
165
. Void
170
may decrease the reliability of the circuit by reducing the conductance and reliability of the aluminum plug
165
or create an open circuit in the semiconductor device being fabricated.
Prior art methods for controlling void formation include, for example, forming openings in the semiconductor wafer with rounded edges, as illustrated in
FIG. 2
a
. Since the edges of opening
230
formed in dielectric layer
220
are rounded, when aluminum layer
260
is sputter deposited and reflowed into opening
230
, as is illustrated in
FIG. 2
b
, the aluminum does not form overhangs and consequently does not pinch the top of opening
230
. As illustrated in
FIG. 2
c
, the remaining aluminum may be sputter deposited and reflowed into opening
230
without the formation of voids or holes.
One problem with forming openings with rounded edges, however, is that they require a larger area (or space) on the surface of the semiconductor device. As can be seen in
FIG. 2
b
, the plug formed using the opening with rounded edges requires additional space on the wafer where a plug formed with vertical sidewalls requires less space on the wafer, as can be seen in
FIG. 1
c
. Consequently this consideration weighs against the formation of smaller and/or more dense semiconductor devices.
Another prior art method for controlling void formation is described in Chen et al., U.S. Pat. No. 5,108,951, issued on Apr. 28, 1992. The process described in Chen et al. uses several process steps. In the first step of Chen et al. aluminum is sputter deposited on the wafer using a cold deposition technique (i.e. less than 350° C.). Next, or in the second step, Chen et al. heats the wafer. As the wafer in Chen et al. is warmed (heated) the aluminum deposited in the cold deposition step, gradually begins to reflow into the opening. Once the wafer in Chen et al. reaches a deposition temperature (i.e. approximately 450° C.) the remaining aluminum is deposited and reflowed into the opening until the opening is completely filled.
One problem with the method described in Chen et al. is that the time required, between the cold deposition step and the relatively hotter deposition step, to heat the wafer decreases the throughput of the system. Additionally, the cold-hot process of Chen et al. exhibits the problems of void formation, described above, in small vias, for example, less than 0.5 micron (<0.5&mgr;).
Other prior art methods use multiple steps to deposit the aluminum, however they use higher temperatures to perform each step. The problem with these techniques and with the hot deposition step of the Chen et al. process is that during these processes the temperatures get too hot, for example, over 450° C., and can cause damage to other underlying layers within the semiconductor device. For example, as temperatures increase this may cause the underlying interlayer dielectrics (ILDs) to crack which may in turn cause reliability problems. Another example is that underlying metal lines may amorphize at the higher temperature causing them to react with surrounding materials and forming compounds upon recooling. Yet another example is that high temperatures may cause high stresses within the underlying films that could lead to delamination of vias tied to those films.
Thus, what is needed is a method for filling an opening having vertical sidewalls in a semiconductor device using a method that reduces or avoids the formation of voids, while maintaining lower temperatures but that allows the formation of relatively more dense and/or smaller semiconductor devices.
SUMMARY OF THE INVENTION
The present invention describes an improved process for forming a metal plug without reaching temperatures that could cause damage to underlying layers during the fabrication of a semiconductor device. An opening is formed in a wafer. The opening is filled with a metal by depositing a first layer of the metal at a first power in a hot deposition chamber and then depositing a second layer of the metal at a second power in a cold deposition chamber.


REFERENCES:
patent: 5108951 (1992-04-01), Chen et al.
patent: 5148259 (1992-09-01), Kato et al.
patent: 5270255 (1993-12-01), Wong
patent: 5356836 (1994-10-01), Chen et al.
patent: 5423939 (1995-06-01), Bryant et al.
patent: 5443995 (1995-08-01), Nulman
patent: 5472912 (1995-12-01), Miller
patent: 5486492 (1996-01-01), Yamamoto et al.
patent: 5523259 (1996-06-01), Merchant et al.
patent: 5527739 (1996-06-01), Parrillo et al.
patent: 5534463 (1996-07-01), Lee et al.
patent: 5633199 (1997-05-01), Fiordalice et al.
patent: 5646449 (1997-07-01), Nakamura et al.
patent

Affiliated with

Also associated with

Rating

Two chamber metal reflow process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Two chamber metal reflow process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two chamber metal reflow process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2830657