Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-08-22
2002-05-21
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
Reexamination Certificate
active
06391802
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to the field of integrated circuits and in particular to integrated capacitors onto a silicon substrate. The present invention relates more particularly to a method of manufacturing an integrated capacitor onto a silicon substrate, comprising a step of depositing a first electrode layer, a step of depositing a dielectric material layer, and a step of depositing a second electrode layer.
2. Description of the Related Art
Nowadays, it is usual practice to design integrated circuits with one or more high value integrated capacitors, which advantageously replace discrete conventional capacitors. Such capacitors have various applications in the field of analog or RF (radiofrequency) circuits, for example for filtering supply voltages, in the design of resonant antenna circuits, etc.
Among the known integrated capacitors, capacitors with metallic electrodes have many advantages compared to capacitors with polysilicon electrodes.
On one hand, metallic electrodes have an excellent electric conductivity, when polysilicon electrodes need, to that effect, a silicide formation process in the presence of a metal like tungsten or titanium.
Capacitors with metallic electrodes are furthermore very easy to manufacture, the lower electrode being generally made from one of the last metallic layers of integrated circuits, for example the metallic layer used to make the upper level conductive tracks or the contact pads. Thus, compared to the conventional method of manufacturing integrated circuits, the design of a capacitor with metallic electrodes only needs a step of depositing, at a low temperature (less than 500° C.), a layer of a dielectric material on a pre-existing metallic layer, used as a first electrode layer, and a step of depositing a second electrode metallic layer. The layers of first and second electrodes are then etched to obtain the desired capacity.
Lastly, capacitors with metallic electrodes have a small parasitic capacity regard to the silicon substrate, because they are made, as just described, on one of the last levels of integrated circuits.
However, in practice, capacitors with metallic electrodes present a poor linearity versus voltage. The linearity versus voltage, or “voltage linearity”, is conventionally defined by the ratio &Dgr;C/C, where C is the value of the capacity at a voltage equal to zero and &Dgr;C the fluctuations of the capacity C according to the applied voltage. The ratio &Dgr;C/C of a capacitor with metallic electrodes is typically in the order of 200 10
−6
/V, i. e. a linearity defect at least 10 times above the value which is generally tolerated by designers of analog integrated circuits.
For this reason, capacitors with metallic electrodes, in spite of the above recalled advantages, have at present few applications only in the field of analog circuits, in particular in the field of RF circuits. The present invention is directed to avoid this drawback.
SUMMARY OF THE INVENTION
Thus, an object of the present invention is to improve the voltage linearity of capacitors formed by a non thermally treated dielectric layer sandwiched between two conductive layers, in particular capacitors with metallic electrodes.
The foregoing objects are achieved as is now described.
After various studies, the authors of the present invention have emitted the hypothesis that the above-mentioned non-linearity phenomenon, which appears a little only in capacitors with polysilicon electrodes, is linked to the fact that capacitors with metallic electrodes, unlike capacitors with polysilicon electrodes, are not subject to an annealing step at a high temperature, conventionally performed with a temperature in the order of 850° C. during several tens of minutes. It is indeed recalled that, in the conventional manufacturing process of integrated circuits, the conventional annealing steps for dopant activation are always performed before depositing the metallic layers, in order not to deteriorate them.
More particularly, the present invention is based on the hypothesis that the poor voltage linearity of capacitors with metallic electrodes is linked to the presence of impurities in the dielectric and/or to an incomplete formation of the dielectric (existence of pendant linkages), which are likely to disappear with a high temperature annealing.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
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Aoyama et al., J. Electrochem. Soc., vol. 143, No. 3, Mar. 1996, pp. 977-983.
Delpech Philippe
Oberlin Jean-Claude
Hoang Quoc
Nelms David
STMicroelectronics S.A.
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