Side wall contact structure and method of forming the same

Details Side wall contact structure and method of forming the same Side wall contact structure and method of forming the same

2001-08-28

2002-05-07

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S396000, C438S397000, C257S306000, C257S311000

Reexamination Certificate

active

06383869

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a side wall contact on a side wall of a contact hole formed in an inter-layer insulator over a semiconductor substrate as well as a method of forming the same.
As the degree of the integration of large scale integrated circuits has been on the increase, each device as integrated has been scaled down. In these circumstances, it is important how a margin between devices is secured without deterioration of a high yield. For example, a self-align-contact or a side wall contact are typical techniques for securing the same.
The side wall contact technique is applicable to various semiconductor devices such as a dynamic random access memory. A conventional method of forming a memory cell structure of the dynamic random access memory will be described.
FIGS. 1A through 1E
are fragmentary cross sectional elevation views illustrative of a conventional method of forming a conventional memory cell structure of a dynamic random access memory, wherein said conventional memory cell structure has a conventional side wall contact structure.
With reference to
FIG. 1A
, field oxide films
2
are selectively formed on a passive region of a p-type silicon substrate
1
to define an active region. Gate oxide films
3
are formed on a part of the field oxide film
2
and the active region of the silicon substrate
1
. First and second gate electrodes
4
of a polysilicon film which also act as word lines are formed on the gate oxide film
3
. The gate electrode
4
is positioned over a channel region in the active region of the substrate
1
. Source and drain diffusion regions
5
of n
−
-type are selectively formed by self-alignment on the active regions other than the channel region of the substrate
1
, whereby the source and drain diffusion regions
5
define the channel region. A first inter-layer insulator
6
is entirely formed which extends over the passive regions and the active regions of the substrate
1
so that the first inter-layer insulator
6
covers the field oxide film
2
, the gate electrodes
4
and the source and drain diffusion regions
5
.
With reference to
FIG. 1B
, a second inter-layer insulator made of boro-phospho silicate glass from tetraethyl orthosilicate (TEOS) is formed on the first inter-layer insulator
6
. The second inter-layer insulator is much thicker than the first inter-layer insulator
6
. Although illustration is omitted, bit contacts and bit lines arc formed. The bit contacts provide electrical connections between the bit lines and the source and drain regions. The bit contacts and the bit lines are formed by well known techniques of photo-lithography and subsequent dry etching. The bit lines may be made of a second polysilicon. A third inter-layer insulator made of boro-phospho silicate glass from tetraethyl orthosilicate (TEOS) is formed on the second inter-layer insulator and over the bit lines, whereby an inter-layer insulator
7
of the second and third inter-layer insulators is then formed. A fourth inter-layer insulator
8
is formed on the inter-layer insulator
7
. The fourth inter-layer insulator
8
may be made of a different insulating material, such as silicon dioxide, from the second and third inter-layer insulators. The fourth inter-layer insulator
8
is much thinner than the inter-layer insulator
7
. The thickness of the fourth inter-layer insulator
8
is, for example, in the range of about 150-200 nanometers. A photo-resist is applied on the fourth inter-layer insulator
8
and then subjected to exposure and subsequent development to form a photo-resist pattern
10
over the fourth inter-layer insulator
8
.
With reference to
FIG. 1C
, a dry etching process is carried out by use of the photo-resist pattern
10
to selectively etch laminations of the fourth inter-layer insulator
8
, the inter-layer insulator
7
and the and the first inter-layer insulator
6
, whereby a contact hole
11
is formed which penetrates the laminations of the fourth inter-layer insulator
8
, the inter-layer insulator
7
and the first inter-layer insulator
6
, so that a part of the diffusion region
5
is shown through the contact hole
11
. The contact hole
11
has a depth of about 1200 nanometers. An oxide film
12
-
a
made of non-doped silicate glass (NSG) from TEOS is entirely deposited so that the oxide film
12
-
a
extends on a bottom and a side wall of the contact hole as well as on the surface of the fourth inter-layer insulator
8
.
With reference to
FIG. 1D
, an etch back to the oxide film
12
-
a
is carried out by use of a dry etching process for the purpose of removing the bottom part of the oxide film
12
-
a
on the diffusion region
5
and also the top parts of the oxide film
12
-
a
on the fourth inter-layer insulator
8
. It is necessary to completely remove the bottom part of the oxide film
12
-
a
so that no residual part of the oxide film
12
-
a
remains on the bottom of the contact hole
11
, whereby the part of the diffusion region
5
is shown through the contact hole
If a diameter of the top portion of the contact hole
11
is about 0.3 micrometers, then an aspect ratio of the contact hole
11
is about 4. This high aspect ratio of the contact hole causes a micro-loading effect which reduces an etching rate of the oxide film
12
-
a
in the deep region of the contact hole
11
. Namely, the micro-loading effect causes the oxide film
12
-
a
over the contact hole
11
to be higher in etching rate than in the deep region of the contact hole
11
. This means that, in order to exactly etch the bottom portion of the oxide film
12
-
a
, it is necessary to allow an over-etching to the upper portion of the oxide film
12
-
a
over the contact hole
11
since the upper portion of the oxide film
12
-
a
is higher in etching rate than the deep portion of the oxide film
12
-
a.
This over-etching to the upper portion of the oxide film
12
-
a
means that not only the top portion of the oxide film
12
-
a
on the surface of the fourth inter-layer insulator
8
but also a shallow portion of the oxide film
12
-
a
positioned in a shallow region of the contact hole
11
are etched, whereby the fourth inter-layer insulator
8
reduces in thickness and thus is made thin, and further the top portion of the oxide film
12
-
a
drops in level so that the top level of the etched oxide film
12
-
a
becomes lower than the bottom level of the fourth inter-layer insulator
8
.
Namely, in order to exactly etch the bottom portion of the oxide film
12
-
a
, the over-etching is continued until the shallower portion of the oxide film
12
-
a
in the shallower region of the contact hole
11
is etched, whereby the oxide film
12
-
a
is made into a side wall contact
12
-
b
which extends on the side wall of the contact hole
11
except on a shallower region of the contact hole
11
. The top portion of the side wall contact
12
-
b
lies lower in level than the bottom of the fourth inter-layer insulator
8
, whereby an upper region of the inter-layer insulator
7
is shown between the top portion of the side wall contact
12
-
b
and the bottom of the fourth inter-layer insulator
8
.
This is caused by the micro-loading effect in the etch-back process under the condition of the high aspect ratio of the contact hole. As the aspect ratio of the contact hole is large, then the micro-loading effect is remarkable, whereby the necessary over-etching amount for completely removing the bottom portion of the oxide film
12
-
a
from the bottom of the contact hole
11
is increased, thereby increasing the amount of drop in level of the top of the side wall contact
11
or the shown region of the inter-layer insulator
7
.
A storage electrode
13
made of polysilicon is then formed which fills the contact hole
11
and extends over the contact hole
11
and the fourth inter-layer insulator
8
. As the requirement for scaling down the storage capacitor increases, it is possible that an alignment of the storage electrode
13
to the contact hole

Affiliated with

Also associated with

Rating

Side wall contact structure and method of forming the same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Side wall contact structure and method of forming the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Side wall contact structure and method of forming the same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2827556