Electronic digital logic circuitry – Significant integrated structure – layout – or layout...
Reexamination Certificate
2001-09-21
2002-09-03
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Significant integrated structure, layout, or layout...
C326S113000, C257S206000
Reexamination Certificate
active
06445214
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit, particularly to a semiconductor integrated circuit applicable to LSI for a general use processor, a signal processing processor, an image processing processor or the like partially including logical operation circuits.
BACKGROUND OF THE INVENTION
Conventionally, in realizing a large scale logical operation circuit, there has widely been used systems of gate array, standard cell (or cell base integrated circuit) and the like. In these integrated circuits, a partial circuit referred to as cell is prepared previously. A cell signifies a small scale logical operation circuit in which layout of a mask pattern has been completed, normally, a plurality of them are arranged on the same chip. In respect of a cell, normally, other than mask layout, positions and areas of input and output terminals, an operational speed, power consumption and the like are prepared. A cell library stores information with regard to the cell in a storage device for assisting design of an integrated circuit. There has been known a design system using such cells, which is combined with a circuit referred to as a pass transistor circuit.
Pass transistor circuits have been introduced as “Differential Pass-transistor Logic” in IEEE Journal of Solid-State Circuits, Vol. sc-22, No. 2, April 1987 pp216-pp222 (hereinafter, referred to as a first conventional technology) and as “Complementary Pass-transistor Logic” in IEEE Journal of Solid-State Circuits, Vol. sc-25, No. 2, April 1990 pp388-pp395 (hereinafter, referred to as a second conventional technology).
Further there has been shown a circuit design method in which a pass transistor circuit is combined with a standard cell system, mentioned above, in Custom Integrated Circuits Conference 1994 Digest pp603-pp606 (hereinafter, referred to as a third conventional technology).
Further, there has also been introduced a design method in which a pass transistor circuit is combined with the standard cell system by utilizing a logical expressing method referred to as “Binary Decision Diagram” in Proceedings of the 1994 IEICE fall conference (basic and boundary region) of the Institute of Electronics, Information and Communication Engineers (IEICE), pp64 (hereinafter, referred to as a fourth conventional technology).
Further, there has been shown a logical operation circuit cell using a pass transistor circuit in Japanese Patent Laid-Open No. 130856/1995 (hereinafter, referred to as a fifth conventional technology).
DISCLOSURE OF THE INVENTION
FIG.
10
and
FIG. 11
illustrate plane views (a) for explaining layout of cells of conventional CMOS logical operation circuits and circuit diagrams thereof (b). Notations p
1001
through p
1003
, n
1001
through n
1003
, p
110
through p
1103
and n
1101
through n
1103
designate transistors. According to the layout of a cell of a CMOS logical operation circuit which has widely been used in a conventional gate array or standard cell system shown by
FIG. 10
or
FIG. 11
, it is general to regularly arrange on a straight line input and output terminals In
1001
through In
1003
and In
1101
through In
1103
for outputting a signal to outside of the cell. This is because in the case of a CMOS logical operation circuit, a portion of a gate can be enlarged on an insulating film (not formed with transistor) present between a first type of a field effect transistor (for example, P-channel MOS) and a second type of a field effect transistor (for example, N-channel MOS) which are in a complementary relationship and accordingly, input and output terminals (In
1001
, In
1002
, In
1003
and Out
10
in
FIG. 10
, In
1101
, In
102
, In
1103
and Out
11
in
FIG. 11
) can easily be enlarged therefrom by a conductor layer.
In the meantime, a pass transistor logical operation circuit cell is constituted by one set or more of pairs of two pass transistors, a gate of each of which responds to a complementary signal and an output signal amplifier. It is a significant feature of a pass transistor logical operation circuit cell that a logical circuit portion and an amplifying circuit portion are separated in this way. In cell layout of such a pass transistor circuit, when input and output terminals are arranged on a straight line similar to a cell of the conventional CMOS logical operation circuit, there poses a problem in which an area efficiency is deteriorated by a restriction of a design rule concerning a conductor layer. Accordingly, in a pass transistor logical operation circuit cell, it is not well known how these input and output terminals are to be arranged.
Further, in laying out a pass transistor logical operation circuit having the above-described constitution, it has not been well known with regard to a problem of how to arrange the output signal amplifier and the pairs of pass transistors.
Further, in the case of laying out a pass transistor logical operation circuit cell having the above-described constitution and a CMOS logical operation circuit cell on the same chip, it has not been well known with regard to how to arrange a semiconductor region surrounding each transistor and having a type reverse to a type of the transistor (for example, n well in the case of pMOS transistor) in the cell.
Further, it has not been well known with regard to at which portion in a layout inside of a cell as well as outside of a cell, a circuit for generating complementary signals provided to respective gates in a pair of two pass transistors in the above-described pass transistor logical operation circuit cell, is to be arranged.
Further, in laying out field effect transistors constituting respectives of a signal polarity inverting circuit for forming complementary signals provided to respective gates of a pair of two pass transistors of the above-described pass transistor logical operation circuit and the above-described output signal amplifier, it has not been well known with regard to at which positions and in what magnitude relationship they are to be laid out.
Therefore, it is an object of the present invention with regard to a cell using a pass transistor circuit, to provide a semiconductor integrated circuit having a layout arrangement of input and output terminals, an output signal amplifier, pairs of pass transistors, well regions and a complementary signal generating circuit capable of reducing an area, reducing a delay time period and facilitating wirings outside of the cell.
In order to achieve the above-described object, a semiconductor integrated circuit according to the present invention is laid out under the following thought.
According to the present invention, there is used a cell having a portion constituted by at least one pass transistor circuit for forming a logic and at least one output signal amplifier. In this case, as a typical example of the present invention, an explanation will be given of a pass transistor logical operation circuit cell in the case in which three of pass transistor circuits are present in respect of a single output signal amplifier. As will be shown later in an embodiment of FIG.
1
through
FIG. 3
, each pass transistor circuit includes a first input node, a second input node and a third input node, an output node, a field effect transistor of a first type or a second type, a source/drain path of which is connected between the first input node and the output node and a field effect transistor of the first type or the second type, a source/drain path of which is connected between the second input node and the output node.
In this case, an output signal amplifier includes a circuit comprising an input node, an output node, a field effect transistor of a first type, a drain/source path of which is connected between the output node and first potential and a gate of which responds to the input node and a field effect transistor of a second type, a drain/source path is connected between the output node and second potential and a gate of which responds to the input node.
The output node of the pass transistor circuit is conne
Rikino Kunihito
Sasaki Yasuhiko
Yamashita Shunzo
Yano Kazuo
Chang Daniel D.
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
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