Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-07
2002-05-21
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S250000, C438S393000, C257S317000
Reexamination Certificate
active
06391716
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a non-volatile memory, and more particularly to an Electron Tunnel Oxide (ETOX) flash memory device with electric-field corners for poly to poly erase.
2. Description of the Prior Art
In conventional ETOX flash memory device, programming and erasing mechanisms are using the same tunnel oxide layer which electrons are transferred through the same tunnel oxide layer and the tunnel oxide layer has been stressed twice in one program/erase cycle. Therefore, the flash memory device will provide less program/erase cycles and a short lifetime. Conventional poly to poly erase flash memory device can solve aforesaid problem by providing another path to avoid transferred electrons through the same tunnel oxide layer twice in one program/erase cycle. However, conventional poly to poly erase flash memory device needs more space to provide for the erase gate and the cell size becomes bigger.
Referring to
FIG. 1A
, the poly spacer ETOX (Electron Tunnel Oxide) flash memory device with poly to poly erase provides a polysilicon spacer
144
as an erase gate, it can prolong the lifetime of the memory device and provide a smaller cell size. A stacking gate electrode
143
comprises a program tunnel oxide layer
120
, a floating gate
140
, a first dielectric
122
, and a control gate
142
on a substrate
100
, and further a source/drain region
110
in the substrate
10
. The polysilicon spacer
144
is separated from the stacking gate electrode
143
and the substrate
100
by an erase tunnel oxide layer
124
. In the programming mechanism, electrons followed the direction
160
are transferred from the substrate
100
through the program tunnel oxide layer
120
to the floating gate
140
and stored in the floating gate
140
. In the erasing mechanism, electrons followed the direction
162
as well as the direction
164
are transferred from the floating gate
140
through the erase tunnel oxide layer
124
to the erase gate electrode
144
.
Referring to
FIG. 2B
, a region
170
is a contact window and a region
169
is an active region. A region
166
is the floating gate
140
and a region
168
is the control gate
142
. In the erasing mechanism, electrons are transferred to the erase gate
144
at corners of the floating gate
140
. Although, it prolong the lifetime of the memory device and provide a smaller cell size. However, it is also important to find a method to raise the efficiency of the program/erase cycle.
SUMMARY OF THE INVENTION
It is an object of the invention that the use of the floating gate having electric field enhancing corners can raise the efficiency of the erasing mechanism.
In accordance with the present invention, a method is provided for forming a poly spacer ETOX (Electron Tunnel Oxide) flash memory device with a floating gate having electric-field enhancing corners for poly to poly erase. First, a substrate has a stacking gate electrode thereon which is formed by following steps. Then, a first polysilicon layer is deposited on the gate oxide layer. Then, a portion of the first polysilicon layer is removed to form polysilicon holes, in which the borders are obliqued to the edges of active regions. Next, a first dielectric layer is deposited on the first polysilicon layer and a second polysilicon layer is deposited on the first dielectric layer. Following, it is proceeded photolithography and etching processes to form a stacking gate electrode which comprising a floating gate having electric-field enhancing corners and a control gate. These field enhancing corners are located at the boundaries of control gate and smaller than 90 degree due to the oblique borders of the first polysilicon holes. The electrical field will be enhanced by these corners, by which, the electron transition from floating gate to erase gate will be easier in erase mode. The stacking gate electrode sequentially comprises a gate oxide layer as program tunnel oxide layer, a first polysilicon layer as the floating gate, a first dielectric layer, and a second polysilicon layer as the control gate on the substrate. Then, a second dielectric layer and a third polysilicon layer are sequentially deposited conformally on the stacking gate electrode and the substrate. Next, a third polysilicon layer is formed a polysilicon spacer by blanket etching which is using the second dielectric layer as a stop layer. Further, the second dielectric layer is blanket etched by using the polysilicon spacer as a hard mask.
REFERENCES:
patent: 6093945 (2000-07-01), Yang
Le Dung Anh
Powell Goldstein Frazer & Murphy LLP
United Microelectronics Corp.
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