Semiconductor fabrication with multiple low dose implant

Details Semiconductor fabrication with multiple low dose implant Semiconductor fabrication with multiple low dose implant

1998-01-07

2002-09-24

Mulpuri, Savitri (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S527000

Reexamination Certificate

active

06455385

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The invention generally relates to semiconductor fabrication, and specifically, the invention relates to substrate doping.
2. Background
Integrated circuits (ICs) are fabricated under very strict processing conditions to ensure predictable and repeatable circuit behavior. The basic building block of typical IC's is the transistor, and particularly the Metal-Oxide-Silicon (MOS) transistor, which has a relatively rapid switching speed.
Referring to the cross-section of
FIG. 1
, MOS devices are formed on a substrate
10
with doped regions
12
and
14
forming source and drain regions, respectively. The doped regions create a n-p-n transistor (
FIG. 1
) or p-n-p transistor (not shown), where the region between the source
12
and drain
14
is known as the “channel” and is generally contained within the boundaries defined by the gate electrode
16
immediately above and separated from the substrate by a dielectric (or insulating region)
18
. The channel is electrically separated from the doped regions
12
and
14
by “junctions”—intrinsic, or carrier depleted, regions in the device where the doping concentration of one type of dopant (n or p) in the channel is equal to the doping concentration of the other type of dopant (n or p) in the adjacent source or drain region. In the case of a n-p-n transistor (shown in
FIG. 1
) carriers from the source-side of the channel are kept from passing through the channel to the drain-side of the channel by the presence of two junctions, namely n-p junction
20
and p-n junction
22
.
The distance between junctions across the channel is commonly referred to as the “channel length.” As is generally known in the art, channel length is one of the key parameters in determining switching speed in MOS devices. Thus, channel lengths are necessarily shrinking in dimensions to accommodate demands for faster IC's.
While in the past, transistor “critical” dimensions were relatively large compared to so called “normal” variation in channel length (i.e., junction positioning), current state-of-the-art technology is much more sensitive to the absolute position of the junctions. For example, a 200 Å channel length variation in a 0.25 micron transistor will have a more significant effect than for the same channel length variation in a 2 micron transistor.
Besides natural variation in junction position, the device designer must consider variation in junction position arising from processing. Such processing induced variation may arise from a difference in the level of doping in the source or drain, or even the channel doping. However, for a fixed channel doping level, the relative amount of doping in the source and drain essentially determines the position of the junctions. If by some mechanism, the doping concentration profile, in the source or drain for example, is different than specified by the designer, the device will behave considerably different than expected. Besides misprocessing, one of the best-known physical mechanisms for unpredictably altering a doping profile is “transient enhanced diffusion” (TED). Another such mechanism, albeit much less understood than TED is “dose-loss”, which refers to the apparently unpredictable “loss” of dopant from specified areas such as sources or drains. From a device designer's perspective, dose loss increases the channel length and decreases the switching speed, while from a process development point-of-view, dose loss increases the resistivity of the doped silicon, possibly beyond an acceptable level. Thus, the elimination, or minimization of dose loss is an important step toward developing a process to reliably increase the speed of today's integrated circuits.
FIGS. 2 and 3
will be used to further illustrate dose loss.
FIG. 2
shows a cross-sectional view of a crystalline substrate
100
. In conventional implantation techniques, dopants
114
are implanted into substrate
100
as indicated by arrows
112
. However, typically subsequent to the implantation step, an anneal (or high temperature treatment) step is generally performed. An anneal is generally a mandatory step in the semiconductor processing domain as an anneal will repair damage to the substrate
100
caused by the implant and activate the doped regions. The dopants tend to diffuse during the anneal steps, and dopants close to the substrate surface may evaporate or diffuse into the surrounding ambient atmosphere.
Often, as shown in
FIG. 3
, a screen oxide
110
is grown or deposited on top of substrate
100
prior to implantation in many conventional processes. Dopants
114
are then implanted through the screen oxide
110
into the substrate
100
as shown by arrows
112
. The screen oxide is useful for reducing dopant “channeling” and confining implant contaminants. However, some of the implant dose remains in the screen oxide
110
. Moreover, as in the anneal step described with respect to
FIG. 1
, although the screen oxide may prevent some dopant “evaporation” into the ambient atmosphere, dopants may still diffuse into the screen oxide so that when the screen oxide is stripped to remove contaminants, a considerable portion of the implanted dose will be lost as well. Thus, dose loss will often occur after an anneal wherein the dopants tend to move from the substrate to the layer adjacent the substrate surface, be that layer the ambient atmosphere, a screen oxide, or otherwise. Such evaporation and/or diffusion can cause a loss of even 50% of the implanted dose.
Dose loss, as described above, has been documented in Griffin, Crowder, and Knight, “Dose Loss in Phosphorous Implants Due to Transient Diffusion and Interface Segregation,” Center for Integrated Systems, Stanford University (Jan. 3, 1995).
Not only does dose loss cause a reduction in dopant concentration in the substrate, but it can also pollute layers that are subsequently formed over the substrate, for instance, the gate oxide, which needs to be as pure as possible for device reliability. Moreover, as mentioned above, controlling the dose and spatial distribution of the dopant in the substrate is critical to device performance and, in particular, is important because dose loss, when unaccounted for, can lead to unpredictable device performance.
SUMMARY OF THE INVENTION
In order to reduce implant dose loss due to evaporation and thermal processes, such as anneal steps, a process in accordance with the invention is disclosed. The process generally entails performing multiple low dose implants with interspersed anneal steps. The anneal steps can be performed at low temperatures in some embodiments of the invention, or at higher temperatures, such as with RTA processes, in other embodiments of the invention. By using a process in accordance with the invention, device reliability and performance will improve, allowing faster integrated circuits to be developed.


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“Dose loss in phosphorus implants due

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