Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-06
2002-09-17
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S595000
Reexamination Certificate
active
06451644
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to an integrated circuit (IC) and the fabrication of an integrated circuit. More particularly, the present invention relates to an integrated circuit having gate electrode material which is highly activated.
BACKGROUND OF THE INVENTION
Ultra-large scale integrated (ULSI) circuits generally include a multitude of transistors, such as, more than one million transistors and even several million transistors on a substrate. The transistors are generally metal oxide semiconductor field effect transistors (MOSFETs), which include a gate conductor disposed between a source region and a drain region. The gate conductor is provided over a thin gate oxide material.
Generally, the gate conductor is a polysilicon or polysilicon/ germanium (Si
x
Ge
(1−x)
) material that controls charge carriers in a channel region between the drain and the source to turn the transistor on and off. The transistors can be N-channel MOSFETs or P-channel MOSFETs.
The polysilicon and polysilicon/germanium gate materials are heavily doped (e.g., P+ or N+) to increase their conductivity. According to conventional processes, the dopant implant projection is positioned at one-half the depth of the gate material (i.e., gate electrode) thickness to reduce the possibility of dopant diffusion through the thin gate oxide into the channel. Dopant diffusion through the thin gate oxide can adversely affect the predictability of the design and the operability of the circuit.
In conventional processes, dopant distribution in the gate material has a Gaussian-like profile (i.e., the dopant concentration is greatest in the center of the gate material). Accordingly, the dopant concentration near the gate electrode/gate oxide interface is relatively low. The relatively low dopant concentration near the gate electrode and gate oxide interface is referred to as “gate-depletion effect” and is a major problem in complementary MOS (CMOS) processes which manufacture small scale transistors.
Conventional processes for fabricating transistors have a limited thermal budget so shallow junctions can be effectively formed. Shallow junctions are necessary for appropriate transistor size in ULSI circuits. Dopant implanted into the gate material is often not sufficiently activated due to the limited thermal budget. The low electrically activated dopant concentration near the gate material/gate oxide interface, combined with the gate depletion effect, causes higher resistance in the polysilicon or polysilicon/germanium gate material. The higher resistance results in a greater voltage drop between the center of the gate electrode/gate oxide. The greater voltage drop causes a loss of effective voltage bias, which in turn degrades MOSFET drive current and speed, and which also increases the power consumed by the transistor.
Thus, there is a need for a process that can manufacture a gate conductor having a box-like dopant profile and achieve high dopant activation. Further still, there is a need for a gate conductor that has a relatively low thermal budget and is not susceptible to gate-depletion effect. Further still, there is a need for a polysilicon/germanium gate conductor that can be efficiently manufactured.
SUMMARY OF THE INVENTION
The present invention relates to a method of manufacturing an integrated circuit. The method includes providing an amorphous semiconductor layer over a dielectric layer, doping the amorphous semiconductor layer, providing a silicide layer over the amorphous semiconductor layer, and annealing the amorphous semiconductor layer to form a crystallized semiconductor layer. Dopants are distributed in the crystallized semiconductor layer in a box-like profile.
The present invention also relates to a method of manufacturing an ultra-large scale integrated circuit including field effect transistors disposed on a semiconductor substrate. Each of the transistors has a gate structure with a gate conductor having a box-like dopant profile. The method includes steps of providing an amorphous silicon layer over a dielectric layer disposed over the substrate, doping the amorphous silicon layer, providing a silicide layer over the amorphous silicon layer, etching the dielectric layer, the amorphous silicon layer, and the silicide layer to form preliminary gate structures, providing nitride spacers for the preliminary gate structures, and laser annealing the amorphous semiconductor layer.
The present invention even further relates to a method of providing a gate structure with a gate conductor having a box-like dopant profile. The method includes providing an amorphous layer over a gate dielectric layer disposed over a substrate, doping the amorphous layer, providing a silicide layer over the amorphous layer, selectively etching the gate dielectric layer, the amorphous layer, and the metal semiconductor layer to form a gate stack, providing spacers for the gate stack, and laser annealing the amorphous layer.
REFERENCES:
patent: 3940289 (1976-02-01), Marquardt et al.
patent: 4063967 (1977-12-01), Graul et al.
patent: 4343832 (1982-08-01), Smith et al.
patent: 4364778 (1982-12-01), Leamy et al.
patent: 4646426 (1987-03-01), Sasaki
patent: 4683645 (1987-08-01), Naguib et al.
patent: 4916090 (1990-04-01), Motai et al.
patent: 5316969 (1994-05-01), Ishida et al.
patent: 5346850 (1994-09-01), Kaschmitter et al.
patent: 5508209 (1996-04-01), Zhang et al.
patent: 5576556 (1996-11-01), Takemura et al.
patent: 5591653 (1997-01-01), Sameshima et al.
patent: 5623157 (1997-04-01), Miyazaki et al.
patent: 5644147 (1997-07-01), Yamazaki et al.
patent: 5648277 (1997-07-01), Zhang et al.
patent: 5719065 (1998-02-01), Takemura et al.
patent: 5767004 (1998-06-01), Balasubramanian et al.
patent: 5798744 (1998-08-01), Tanaka et al.
patent: 5804878 (1998-09-01), Miyazaki et al.
patent: 5817550 (1998-10-01), Carey et al.
patent: 5818070 (1998-10-01), Yamazaki et al.
patent: 5882962 (1999-03-01), Tseng et al.
patent: 5945711 (1999-08-01), Takemura et al.
patent: 5962872 (1999-10-01), Zhang et al.
patent: 5962897 (1999-10-01), Takemura et al.
patent: 6127216 (2000-10-01), Yu
S. L. Wu et al., Suppression of the Boron Penetration Induced Si/SiO2 Interface Degradation by Using a Stacked-Amorphous-Silicon Film as the Gate Structure for pMOSFET. 1994, IEEE, pp. 160-162.*
B. Yu et al., CMOS Transistor Reliability and Performance Impacted by Gate Microstructure. 1997, IEEE, pp. 35-41.*
J. Yi et al., Amorphous and Micro-Crystalline Silicon for Photovoltaic Application. 1993, IEEE, pp. 977-980.
Chaudhuri Olik
Duy Mai Anh
Foley & Lardner
LandOfFree
Method of providing a gate conductor with high dopant... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of providing a gate conductor with high dopant..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of providing a gate conductor with high dopant... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2816737