Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2008-01-29
2008-01-29
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S626000, C438S633000, C438S638000, C438S740000, C257SE21579
Reexamination Certificate
active
07323407
ABSTRACT:
Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a via with a hydrogen silsesquioxane (HSQ)-based filler as expressed by the general chemical formula: (RSiO3/2)x(HSiO3/2)y, wherein x and y satisfy the relationships x+y=1 and 0<x<y<1, and R is selected from C4-C24 alkyl, C4-C24 alkenyl, C4-C24 alkoxy, C8-C24 alkenoxy, substituted C4-C24 hydrocarbon, non-substituted C1-C4 hydrocarbon or substituted C1-C4 hydrocarbon; and, partially etching the filler filling the via and an interlayer dielectric to form a trench, which is connected to the via in the region where the dual damascene interconnections are to be formed. Then, the filler remaining in the via is removed, and the trench and the via are filled with an interconnection material to complete the dual damascene interconnections.
REFERENCES:
patent: 6352945 (2002-03-01), Matsuki, et al.
patent: 6383955 (2002-05-01), Matsuki, et al.
patent: 6410463 (2002-06-01), Matsuki
patent: 6432846 (2002-08-01), Matsuki
patent: 6440872 (2002-08-01), Mandelman, et al.
patent: 6455445 (2002-09-01), Matsuki
patent: 6461955 (2002-10-01), Tsu, et al.
patent: 6514880 (2003-02-01), Matsuki, et al.
patent: 6559520 (2003-05-01), Matsuki, et al.
patent: 6858528 (2005-02-01), Meagley et al.
patent: 6898851 (2005-05-01), Nishioka et al.
patent: 7018920 (2006-03-01), Meagley et al.
patent: 2004/0058538 (2004-03-01), Park, et al.
patent: 2004/0132291 (2004-07-01), Lee, et al.
patent: 2004/0183203 (2004-09-01), Meagley et al.
patent: 2005/0124152 (2005-06-01), Meagley et al.
patent: 10-1999-0003782 (1999-02-01), None
patent: 2003-0048454 (2003-06-01), None
patent: 1020040010130 (2004-01-01), None
patent: WO 02/37542 (2001-05-01), None
Kim Jae-Hak
Lee Kyoung-Woo
Maeng Jae-yeol
Oh Il-whan
Shin Hong-jae
Fourson George
Mills & Onello LLP
Samsung Electronics Co,. Ltd
LandOfFree
Method of fabricating dual damascene interconnections of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating dual damascene interconnections of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating dual damascene interconnections of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2814739