Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-01-29
2008-01-29
Baumeister, B. William (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S589000, C257S256000
Reexamination Certificate
active
07323386
ABSTRACT:
A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and may be electrically connected to the source region. When the MOSFET is reverse-biased, depletion regions extend from the dielectric sidewall spacers into the “drift” region, shielding the gate oxide from high electric fields and increasing the avalanche breakdown voltage of the device. This permits the drift region to be more heavily doped and reduces the on-resistance of the device. It also allows the use of a thin, 20 Å gate oxide for a power MOSFET that is to be switched with a 1V signal applied to its gate while being able to block over 30V applied across its drain and source electrodes, for example.
REFERENCES:
patent: 4957881 (1990-09-01), Crotti
patent: 5168331 (1992-12-01), Yilmaz
patent: 5216275 (1993-06-01), Chen
patent: 5244823 (1993-09-01), Adan
patent: 5349224 (1994-09-01), Gilbert et al.
patent: 5960277 (1999-09-01), Blanchard
patent: 6342709 (2002-01-01), Sugawara et al.
patent: 6590240 (2003-07-01), Lanois
patent: 6635534 (2003-10-01), Madson
patent: 6750507 (2004-06-01), Williams et al.
patent: 7038260 (2006-05-01), Yo
patent: 2002/0030237 (2002-03-01), Omura et al.
patent: 2003/0096464 (2003-05-01), Lanois
patent: 2004/0031987 (2004-02-01), Henninger et al.
patent: 2004/0084721 (2004-05-01), Kocon et al.
patent: 2005/0167695 (2005-08-01), Yilmaz
patent: 2005/0167744 (2005-08-01), Yilmaz
patent: 2005/0173758 (2005-08-01), Peake et al.
patent: 2006/0049453 (2006-03-01), Schmitz et al.
patent: 1073110 (2001-01-01), None
patent: 1369927 (2003-12-01), None
patent: 07142713 (1995-06-01), None
patent: 08102538 (1996-04-01), None
Jongdae Kim et al., “High-Density Trench DMOSFETs Employing Two Step Trench Technique and Trench Contact Structure”, ISPSD-2003 Proceedings, pp. 1-4.
Il-Yong Park et al., “Novel Process Techniques for Fabricating High Density Trench MOSFETs with Self-Aligned N+/P+Source Formed on the Trench Side Wall”, ISPSD-2003 Proceedings, pp. 1-4.
M.A.A. in {grave over (t)}Zandt, et al., “Record-low 4mΩ mm2specific on-resistance for 20V Trench MOSFETs”, ISPSD-2003 Proceedings, pp. 1-4.
Mohamed Darwish et al., “A New Power W-Gated Trench MOSFET (WMOSFET) with High Switching Performance”, ISPSD-2003 Proceedings, pp. 1-4.
Syotaro Ono et al., “30V New Fine Trench MOSFET with Ultra Low On-Resistance”, ISPSD-2003 Proceedings, pp. 1-4.
Gupta, R.N. et al., A Novel Planarized Silicon Trench Sidewall Oxide Merged p-i-n Schottky (TSOX-MPS) Rectified, IEEE Electron Device Letters, vol. 20, No. 12, Dec. 1999.
Chang, H.R. et al. Development and Demonstration of Silicon Carbide (SiC) Motor Drive Inverter Modules, 2003, IEEE 34thAnnual Power Electronics Specialists Conference (PESC) Conference Proceedings, Acapulco, Mexico, Jun. 15, 2003.
Baumeister B. William
Patentability Associates
Wagner Jenny L.
LandOfFree
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